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參數(shù)資料
| 型號(hào)： | AM29N323DT11AWKI |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| 中文描述： | 32兆位（2米× 16位）的CMOS 1.8伏，只有同時(shí)讀/寫，突發(fā)模式閃存 |
| 文件頁數(shù)： | 47/48頁 |
| 文件大?。?/td> | 824K |
| 代理商： | AM29N323DT11AWKI |
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46
Am29N323D
August 8, 2002
REVISION SUMMARY
Notice: This document is not intended for
public release, and is differentiated from
the publicly released version by an “N” in
the publication number. For information
on the publicly released device, the
Am29BDS323, refer to publication 23476,
available at http://www.amd.com/prod-
ucts/nvd/techdocs/23476.pdf.
Revision A (February 15, 2000)
Limited, non-public release.
Revision B (June 20, 2000)
Public release, with the following changes:
Block Diagram
Corrected address range to A0–A20.
Ordering Information
Deleted reference to 54 MHz speed option.
Device Bus Operations table
Split address range column into two columns.
AC Characteristics
Asynchronous Read:
In table, changed “falling” to
“rising” in description of t
AAVDS
. In diagram, modified
t
AAVDS
and t
AAVDH
waveforms to reference from the
rising edge of AVD#.
Synchronous/Burst Read table:
Added t
RDYS
, t
CEH
specifications.
Erase/Program Operations table, Program Operations
Timings figure, Chip/Sector Erase Operations Timings
figure:
Added t
AVDP
. Added PS waveforms to program
operations timings figure.
Initial Access with Power Savings (PS) and
Address Boundary Latency figure
Modified D0 data to extended to D1.
Erase and Programming Performance
Added typical and maximum accelerated chip pro-
gramming time.
Revision B+1 (August 11, 2000)
Chip Erase Command Sequence
Corrected the command sequence length during
unlock bypass mode from four cycles to two.
Revision B+2 (November 27, 2000)
Global
Changed all 9A (speed option) references to 90A.
Accelerated Program Operation, Program
Command Sequence
Added text indicating that sectors must be unlocked
prior to raising V
PP
to V
ID
.
AC Characteristics
Figure 9
, Burst Mode Read:
Corrected RDY waveform
to indicate when PS is enabled, and when RDY is in the
high impedance state.
Figure 14
, Accelerated Unlock Bypass Programming
Timing:
Modified Note 3 to indicate that sectors must
be unlocked prior to raising V
PP
to V
ID
.
Revision B+3 (November 30, 2000)
Figure 10
, Asynchronous Mode Read
Corrected endpoint for t
AAVDS
specification.
Figure 16
, Toggle Bit Timings
(During Embedded Algorithm)
Corrected OE# waveform during second VA (valid
address) period.
Revision B+4 (December 21, 2000)
Figure 9
, Burst Mode Read
Corrected RDY waveform.
Revision B+5 (March 7, 2001)
Global
The 90 ns asynchronous access time specification has
changed to 110 ns. Note that the device now has a new
ordering part number and a new package marking.
Input/Output Descriptions, RESET#: Hardware
Reset Input
Noted that RESET# must be asserted low during
device power-up.
Autoselect Command Sequence
Added extended device ID explanatory text.
Sector Erase Command Sequence, DQ7: Data#
Polling, and DQ6: Toggle Bit I
Added explanatory text to indicate 200 μs wait for first
status read occurring in a different bank than the last
sector selected for erasure in a multiple bank sector
erase command sequence.
Table 4
, Command Definitions
Added the extended device ID code to table. Added
corresponding note below table.
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