參數(shù)資料
型號(hào)： AM79C961AKIW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132
封裝： PLASTIC, QFP-132
文件頁(yè)數(shù)： 115/206頁(yè)
文件大?。?/td> 1507K
代理商： AM79C961AKIW
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Am79C961A
115
matically incriminated by 1 or 2
when byte or word accesses,
respectively, are performed to
the
SRAMDP
(ISACSR0).
register
ISACSR2: Miscellaneous Configuration 1
Bit
Name
Description
15MODE_STATUS
Mode Status. This is a read-only
register which indicates whether
the PCnet-ISA II is configured in
slave mode. A set condition indi-
cates slave mode while a clear
condition indicates bus-master
condition.
10BASE-T External Loop back
Enable. This bit is usable only
when 10BASE-T is selected
AND PCnet-ISA II is in external
loop back. External loop back is
set during initialization via the
MODE
register.
TMAU_LOOPE is set, a board
level test is enabled via a loop
back
clip
which
10BASE-T RJ45 transmit pair to
the receiver pair. This will test all
external components (i.e. trans-
formers, resistors, etc.) of the
10BASE-T
path.
LOOPE assertion is not suitable
for live network tests. When
TMAU_LOOPE is deasserted,
default condition, external loop
back in 10BASE-T is allowed.
Programmed I/O Select. When
operating in the Bus Slave mode
with this bit reset to ZERO, a
shared memory implementation
is selected and the local SRAM
is accessible through memory
cycles on the ISA bus interface.
When operating in the Bus Slave
mode with this bit set to ONE, a
Programmed I/O implementa-
tion is selected and the local
SRAM is accessible through I/O
cycles on the ISA bus interface.
Refer to the Shared Memory and
Programmed I/O sections for
details on these two architecture
schemes.
When operating in the Bus Master
mode, this bit has no effect.
PIOSEL is reset to ZERO.
Slot Identification. This is a
read-only register bit which indi-
cates if PCnet-ISA II is either in
an 16 or 8 bit slot. Reading a one
indicates an 8 bit slot. Zero indi-
14 TMAU_LOOPE
When
ties
the
TMAU_
13
PIOSEL
12
SLOT_ID
cates a 16-bit slot. (SLOT_ID bit
is not valid after the INIT bit is set
in CSR0.)
ISA Protect. When set, the
ISACSR
’
s 0
–
2 and 4
–
9 are
protected from being written
over by software drivers. When
ISA_ PROTECT is cleared,
ISACSR
’
s 0
–
2 and 4
–
9 are
allowed to be written over by
software and reset by reading
the Software reset I/O location.
(Default is zero)
EISA Decode. This control bit
allows EISA product identifier reg-
isters 12-bit decode xC80 - xC83
(4 Bytes). Default is zero.
Plug and Play Active. When
this bit is set, PCnet-ISA II will
become active after serially
reading the EEPROM. If check
sum failure exist, PCnet-ISA II
will not become active and
alternate access method to
Plug and Play registers will
occur. Default is zero.
Address PROM Write Enable. It
is reset to zero by RESET. When
asserted, this pin allows write
access to the internal Address
PROM RAM. APWEN is used
also to protect the Flash device
from write cycles. When pro-
gramming of the Flash device is
required, the APWEN bit needs
to be set. When reset, this pin
protects the internal Address
PROM RAM, and external Flash
device from being overwritten.
EISA Level. This bit is a
read-only register. It indicates if
the level or edge sensitive inter-
rupts have been selected. A set
condition indicates level sensi-
tive interrupts. A clear condition
indicates ISA edge.
Disable Staggered Data Bus.
When this bit is a zero, the data
bus driver timing is staggered
from the address bus driver
timing in Bus Master mode.
When this bit is a one, the data
bus is not staggered. It is similar
to the PCnet-ISA
(Am79C960)
timing. This bit is reset to zero.
For most applications, this bit
should not have to be set.
11 ISA_PROTECT
10 EISA_DECODE
9
P&P_ACT
8
APWEN
7
EISA_LVL
6
DSDBUS
5 10BASE5_SEL
10BASE5 Select. When set, this
bit inverts the polarity of the DX-
CVR pin only when the AUI port
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