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參數(shù)資料
| 型號： | AM79C961AKIW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數(shù)： | 192/206頁 |
| 文件大?。?/td> | 1507K |
| 代理商： | AM79C961AKIW |
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192
Am79C961A
Note:
The labels in the following text are used as references in the
timeline diagram that follows.
SETUP:
The driver should set up descriptors in groups of 3, with
the OWN and STP bits of each set of three descriptors
to read as follows: 11b, 10b, 00b.
An option bit (LAPPEN) exists in CSR3, bit position 5.
The software should set this bit. When set, the LAPPEN
bit directs the PCnet-ISA II to generate an INTERRUPT
when STP has been written to a receive descriptor by
the PCnet-ISA II controller.
FLOW:
The PCnet-ISA II controller polls the current receive
descriptor at some point in time before a message
arrives. The PCnet-ISA II controller determines that
this receive buffer is OWNed by the PCnet-ISA II
controller and it stores the descriptor information to
be used when a message does arrive.
N0: Frame preamble appears on the wire, followed by
SFD and destination address.
N1: The 64th byte of frame data arrives from the wire.
This causes the PCnet-ISA II controller to begin
frame data DMA operations to the first buffer.
C0: When the 64th byte of the message arrives, the
PCnet-ISA II controller performs a lookahead oper-
ation to the next receive descriptor. This descriptor
should be owned by the PCnet-ISA II controller.
C1: The PCnet-ISA II controller intermittently requests
the bus to transfer frame data to the first buffer as
it arrives on the wire.
S0: The driver remains idle.
C2: When the PCnet-ISA II controller has completely
filled the first buffer, it writes status to the first
descriptor.
C3: When the first descriptor for the frame has been
written, changing ownership from the PCnet-ISA II
controller to the CPU, the PCnet-ISA II controller
will generate an SRP INTERRUPT. (This inter-
rupt appears as a RINT interrupt in CSR0.)
S1: The SRP INTERRUPT causes the CPU to switch
tasks to allow the PCnet-ISA II controller
’
s driver
to run.
C4: During the CPU interrupt-generated task switch-
ing, the PCnet-ISA II controller is performing a
lookahead operation to the third descriptor. At this
point in time, the third descriptor is owned by the
CPU.
[
Note:
Even though the third buffer is not
owned by the PCnet-ISA II controller, existing
AMD Ethernet controllers will continue to perform
data DMA into the buffer space that the controller
already owns (i.e. buffer number 2). The controller
does not know if buffer space in buffer number 2
will be sufficient or not, for this frame, but it has no
way to tell except by trying to move the entire mes-
sage into that space. Only when the message
does not fit will it signal a buffer error condition
—
there is no need to panic at the point that it discov-
ers that it does not yet own descriptor number 3.]
S2: The first task of the driver
’
s interrupt service
routine is to collect the header information from
the PCnet-ISA II controller
’
s first buffer and pass it
to the application.
S3: The application will return an application buffer
pointer to the driver. The driver will add an offset
to the application data buffer pointer, since the
PCnet-ISA II controller will be placing the first
portion of the message into the first and second
buffers. (The modified application data buffer
pointer will only be directly used by the PCnet-ISA
II controller when it reaches the third buffer.) The
driver will place the modified data buffer pointer
into the final descriptor of the group (#3) and will
grant ownership of this descriptor to the PC-
net-ISA II controller.
C5: Interleaved with S2, S3 and S4 driver activity, the
PCnet-ISA II controller will write frame data to
buffer number 2.
S4: The driver will next proceed to copy the contents
of the PCnet-ISA II controller
’
s first buffer to the
beginning
of the application space. This copy will
be to the exact (unmodified) buffer pointer that
was passed by the application.
S5: After copying all of the data from the first buffer
into the beginning of the application data buffer,
the driver will begin to poll the ownership bit of the
second descriptor. The driver is waiting for the
PCnet-ISA II controller to finish filling the second
buffer.
C6: At this point, knowing that it had not previously
owned the third descriptor, and knowing that the
current message has not ended (there is more
data in the fifo), the PCnet-ISA II controller will
make a
“
last ditch lookahead
”
to the final (third)
descriptor; This time, the ownership will be TRUE
(i.e. the descriptor belongs to the controller),
because the driver wrote the application pointer
into this descriptor and then changed the owner-
ship to give the descriptor to the PCnet-ISA II con-
troller back at S3. Note that if steps S1, S2 and S3
have not completed at this time, a BUFF error will
result.
C7: After filling the second buffer and performing the
last chance lookahead to the next descriptor, the
PCnet-ISA II controller will write the status and
change the ownership bit of descriptor number 2.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C961APDLUTS | 制造商:Advanced Micro Devices 功能描述: |
| AM79C961AVC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Advanced Micro Devices 功能描述:LAN Node Controller, 144 Pin, TQFP |
| AM79C961AVC/W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C961AVC\\W | 制造商:Rochester Electronics LLC 功能描述: |
| AM79C961AVC\W | 制造商:Rochester Electronics LLC 功能描述: |
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