參數(shù)資料
型號： AM79C961AKIW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132
封裝： PLASTIC, QFP-132
文件頁數(shù)： 117/206頁
文件大?。?/td> 1507K
代理商： AM79C961AKIW
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Am79C961A
117
EE_EN, for detailed use of this
bit).
EEPROM Chip Select. EECS
asserts the chip select to the
Serial EEPROM. (Refer to Bit 4
above, EE_EN, for detailed use
of this bit).
Serial Shift Clock. SK controls
the SK input to the Serial EE-
PROM and the optional External
Shift Logic. (Refer to Bit 4 above,
EE_EN, for detailed use of this
bit).
Serial Shift Data In and Serial
Shift Data Out. When written,
this bit controls the DI input of
the serial EEPROM. When read,
this bit represents the DO value
of the serial EEPROM. (Refer to
Bit 4 above, EE_EN, for detailed
use of this bit).
2
EECS
1
SK
0
DI/DO
ISACSR4: LED0 Status (Link Integrity)
Bit
Name
Description
ISACSR4 is a non-programm-
able register that uses one bit to
reflect the status of the LED0
pin. This pin defaults to twisted
pair MAU Link Status (LNKST)
and is not programmable.
10BASE-T Link Status. LNKST
is a read-only bit that indicates
whether the Link Status LED is
asserted. When LNKST is read
as zero, the Link Status LED is
not asserted. When LNKST is
read as one, the Link Status LED
is asserted, indicating good
10BASE-T link integrity.
Note that the LNKST LED is
masked if the 10BASE-T port is
operating in Full Duplex mode,
AUIFD (ISACSR9, bit 1) is
cleared, and any one of the
FDLSE bits is set in ISACSR5,
6, or 7. Hence, an adapter card
with a 10BASE2 port (through
the AUI port) and a 10BASE-T
port that can be software
enabled for Half or Full Duplex
operation can have a Half
Duplex Link Status LED and a
Full Duplex Link Status LED in
which only one will be allowed
ON, depending on if FDEN
(ISACSR9, bit 0) is set. 14-0
RESReserved locations. Written
as zero, read as undefined.
15
LNKST
14-0
RES
Reserved locations. Written as
zero, read as undefined.
ISACSR5: LED1 Status
Bit
Name
Description
ISACSR5 controls the function(s)
that the LED1 pin displays. Multi-
ple functions can be simulta-
neously enabled on this LED pin.
The LED display will indicate the
logical OR of the enabled func-
tions. ISACSR5 defaults to
Receive Status (RCV) with pulse
stretcher enabled (PSE = 1) and
is fully programmable.
Indicates
the
stretched) state of the function(s)
generated. Read only.
Reserved locations. Read and
written as zero.
Magic Packet LED Enable.
When set, the LED output will be
asserted to indicate that a Magic
Packet has been received.
Full Duplex Link Status Enable.
Indicates the Full Duplex Link
Test Status. When this bit is set,
a value of ONE is passed to the
LEDOUT signal when the PC-
net-ISA II is functioning in a link
pass state with Full Duplex ca-
pability. When the PCnet-ISA II
is not functioning in a link pass
state with Full Duplex capability,
a value of ZERO is passed to the
LEDOUT signal.
When the 10BASE-T port is
active, a value of ONE is passed
to the LEDOUT signal whenever
the Link Test Function (described
in the T-MAU section) detects a
Link Pass state and the FDEN
(ISACSR9, bit 0) bit is set. When
the AUI port is active, a value of
ONE is passed to the LEDOUT
signal whenever Full Duplex oper-
ation on the AUI port is enabled
(both FDEN and AUIFD bits in
ISACSR9 are set to ONE). When
the GPSI port is active, a value of
ONE is passed to the LEDOUT
signal whenever Full Duplex oper-
ation on the GPSI port is enabled
(FDEN bit in ISACSR9 is set to
ONE).
Pulse Stretcher Enable. Extends
the LED illumination for each
enabled function occurrence.
15
LEDOUT
current
(non-
14-10
RES
9
MP
8
FDLSE
7
PSE
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