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參數(shù)資料
| 型號(hào)： | AM79C975 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| 中文描述： | PCnet⑩快速三單芯片10/100 Mbps的PCI以太網(wǎng)控制器集成PHY |
| 文件頁(yè)數(shù)： | 136/304頁(yè) |
| 文件大小： | 2092K |
| 代理商： | AM79C975 |
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136
Am79C973/Am79C975
P R E L I M I N A R Y
through the MAPINT (CSR7, bit
6) interrupt or the MCCIINTE is
set to 1.
Read/Write accessible always.
MCCINTE is set to 0 by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
3
MCCIINT
PHY Management Command
Complete Internal Interrupt. The
PHY Management Command
Complete Interrupt is set by the
Am79C973/Am79C975 controller
when a read or write operation on
the internal PHY management
port is complete from an internal
operation. Examples of internal
operations are Auto-Poll or PHY
Management
Port
management frames. These are
normally hidden to the host.
generated
When MCCIINT is set to 1, INTA
is asserted if the enable bit MC-
CINTE is set to 1.
Read/Write accessible always.
MCCIINT is cleared by the host
by writing a 1. Writing a 0 has no
effect. MCCIINT is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
2
MCCIINTE
PHY Management Command
Complete Internal Interrupt En-
able. If MCCIINTE is set to 1, the
MCCIINT bit will be able to set
the INTR bit when the internal
state machines generate man-
agement frames. For instance,
when MCCIINTE is set to 1 and
the Auto-Poll state machine gen-
erates a management frame, the
MCCIINT will set the INTR bit
upon completion of the manage-
ment frame regardless of the
comparison outcome.
Read/Write accessible always.
MCCIINTE is set to 0 by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
1
MIIPDTINT PHY Detect Transition Interrupt.
The PHY Detect Transition Inter-
rupt is set by the Am79C973/
Am79C975 controller whenever
the MIIPD bit (BCR32, bit 14)
transitions from 0 to 1 or vice ver-
sa.
Read/Write accessible always.
MIIPDTINT is cleared by the host
by writing a 1. Writing a 0 has no
effect. MIIPDTINT is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
0
MIIPDTINTE PHY Detect Transition Interrupt
Enable. If MIIPDTINTE is set to 1,
the MIIPDTINT bit will be able to
set the INTR bit.
Read/Write accessible always.
MIIPDTINTE is set to 0 by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
CSR8: Logical Address Filter 0
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
LADRF[15:0] Logical Address Filter, LADRF-
[15:0]. The content of this register
is undefined until loaded from the
initialization block after the INIT
bit in CSR0 has been set or a di-
rect register write has been per-
formed on this register.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
CSR9: Logical Address Filter 1
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0 LADRF[31:16] Logical Address Filter, LADRF-
[31:16]. The content of this regis-
ter is undefined until loaded from
the initialization block after the
INIT bit in CSR0 has been set or
a direct register write has been
performed on this register.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C973 | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973KCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975KCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973VCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975VCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C975BKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKC\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKD\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKD\W | 制造商:Advanced Micro Devices 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY 制造商:AMD (Advanced Micro Devices) 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975BKDW | 制造商:Advanced Micro Devices 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY 制造商:AMD (Advanced Micro Devices) 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
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