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參數(shù)資料
| 型號： | AM79C975 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| 中文描述： | PCnet⑩快速三單芯片10/100 Mbps的PCI以太網(wǎng)控制器集成PHY |
| 文件頁數(shù)： | 87/304頁 |
| 文件大小： | 2092K |
| 代理商： | AM79C975 |
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Am79C973/Am79C975
87
P R E L I M I N A R Y
nals and to mitigate carrier fade in the event of worst
case signal attenuation and crosstalk noise conditions.
Figure 38. 10BASE-T Transmit and Receive Data
Paths
Twisted Pair Interface Status
The Am79C973/Am79C975 device will power up in the
Link Fail state. The Auto-Negotiation algorithm will
apply to allow it to enter the Link Pass state.
In the Link Pass state, receive activity which passes the
pulse width/amplitude requirements of the RX± inputs,
will cause the PCS Control block to assert Carrier
Sense (CRS) signal at the internal MII interface. Colli-
sion would cause the PCS Control block to assert Car-
rier Sense (CRS) and Collision (COL) signal at the
internal MII. In the Link Fail state, this block would
cause the PCS Control block to de-assert Carrier
Sense (CRS) and Collision (COL).
In jabber detect mode, this block would cause the PCS
Control block to assert the COL pin at the MII, and
allow the PCS Control block to assert or de-assert the
CRS pin to indicate the current state of the RX± pair. If
there is no receive activity on RX±, this block would
cause the PCS Control block to assert only the COL pin
at the internal MII. If there is RX± activity, this block
would cause the PCS Control block to assert both COL
and CRS at the internal MII.
Collision Detect Function
Simultaneous activity (presence of valid data signals)
from both the internal encoder transmit function and
the twisted pair RX± pins constitutes a collision,
thereby causing the PCS Control block to assert the
COL pin at the internal MII.
Jabber Function
The Jabber function inhibits the 10BASE-T twisted pair
transmit function of the Am79C973/Am79C975 device
if the TX± circuits are active for an excessive period
(20-150 ms). This prevents one port from disrupting the
network due to a
stuck-on
or faulty transmitter condi-
tion. If the maximum transmit time is exceeded, the
data path through the 10BASE-T transmitter circuitry is
disabled (although Link Test pulses will continue to be
sent). The PCS Control block also asserts the COL pin
at the internal MII and sets the Jabber Detect bit in
Register 1. Once the internal transmit data stream from
the MENDEC stops, an
unjab
time of 250-750 ms will
elapse before this block causes the PCS Control block
to de-assert the COL indication and re-enable the
transmit circuitry.
When jabber is detected, this block will cause the PCS
control block to assert the COL pin and allow the PCS
Control block to assert or de-assert the CRS pin to in-
dicate the current state of the RX± pair. If there is no re-
ceive activity on RX±, this block causes the PCS
Control block to assert only the COL pin at the internal
MII. If there is RX± activity, this block will cause the
PCS Control block to assert both COL and CRS at the
internal MII.
Reverse Polarity Detect
The polarity for 10BASE-T signals is set by reception of
Normal Link Pulses (NLP) or packets. Polarity is
locked, however, by incoming packets only. The first
NLP received when trying to bring the link up will be ig-
nored, but it will set the polarity to the correct state. The
reception of two consecutive packets will cause the po-
larity to be locked, based on the polarity of the ETD. In
order to change the polarity once it has been locked,
the link must be brought down and back up again.
Auto-Negotiation
The object of the Auto-Negotiation function is to deter-
mine the abilities of the devices sharing a link. After ex-
changing abilities, the Am79C973/Am79C975 device
and remote link partner device acknowledge each
other and make a choice of which advertised abilities to
support. The Auto-Negotiation function facilitates an
ordered resolution between exchanged abilities. This
exchange allows both devices at either end of the link
to take maximum advantage of their respective shared
abilities.
Clock
Data
Manchester
Encoder
Clock
Data
Manchester
Decoder
Squelch
Circuit
RX Driver
RX
±
TX
±
TX Driver
21510D-43
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C973 | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973KCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975KCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973VCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975VCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C975BKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKC\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKD\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKD\W | 制造商:Advanced Micro Devices 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY 制造商:AMD (Advanced Micro Devices) 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975BKDW | 制造商:Advanced Micro Devices 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY 制造商:AMD (Advanced Micro Devices) 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
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