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參數(shù)資料
| 型號(hào)： | AM79C975 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| 中文描述： | PCnet⑩快速三單芯片10/100 Mbps的PCI以太網(wǎng)控制器集成PHY |
| 文件頁(yè)數(shù)： | 173/304頁(yè) |
| 文件大?。?/td> | 2092K |
| 代理商： | AM79C975 |
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Am79C973/Am79C975
173
P R E L I M I N A R Y
The access time for the Expan-
sion ROM or for the EBDATA
(BCR30) device (t
ACC)
during
write operations can be calculat-
ed by subtracting the clock to out-
put delay for the EBUA EBA[7:0]
outputs
(t
v_A_D
) and by adding
the input to clock setup time for
Flash/EPRO inputs (t
s_D
) from
the time defined by ROMTMG.
t
ACC
= ROMTMG * CLK period *
CLK_FAC - (t
v_A_D
) - (t
s_D
)
For an adapter card application,
the value used for clock period
should be 30 ns to guarantee cor-
rect interface timing at the maxi-
mum clock frequency of 33 MHz.
Read accessible always; write
accessible only when the STOP
bit is set. ROMTMG is set to the
value of 1001b by H_RESET and
is not affected by S_RESET or
STOP. The default value allows
using an Expansion ROM with an
access time of 250 ns in a system
with a maximum clock frequency
of 33 MHz.
11
NOUFLO
No Underflow on Transmit. When
the NOUFLO bit is set to 1, the
Am79C973/Am79C975 controller
will not start transmitting the pre-
amble for a packet until the
Transmit Start Point (CSR80, bits
10-11) requirement (except when
XMTSP = 3h, Full Packet has no
meaning when NOUFLO is set to
1) has been met
and
the com-
plete packet has been DMA
’
d into
the Am79C973/Am79C975 con-
troller. The complete packet may
reside in any combination of the
Bus Transmit FIFO, the SRAM,
and the MAC Transmit FIFO, as
long as enough of the packet is in
the MAC Transmit FIFO to meet
the Transmit Start Point require-
ment. When the NOUFLO bit is
cleared to 0, the Transmit Start
Point is the only restriction on
when preamble transmission be-
gins for transmit packets.
Setting the NOUFLO bit guaran-
tees
that
the
Am79C975 controller will never
Am79C973/
suffer transmit underflows, be-
cause the arbiter that controls
transfers to and from the SRAM
guarantees a worst case latency
on transfers to and from the MAC
and Bus Transmit FIFOs such
that it will never underflow if the
complete
packet
DMA
’
d into the Am79C973/
Am79C975
controller
packet transmission begins.
has
been
before
The NOUFLO bit has no effect
when the Am79C973/Am79C975
controller is operating in the NO-
SRAM mode.
Read/Write accessible only when
either the STOP or the SPND bit
is set. NOUFLO is cleared to 0 af-
ter H_RESET or S_RESET and
is unaffected by STOP.
10
RES
Reserved location. Written as ze-
ros and read as undefined.
9
MEMCMD
Memory Command used for burst
read accesses to the transmit
buffer. When MEMCMD is set to
0, all burst read accesses to the
transmit buffer are of the PCI
command type Memory Read
Line (type 14). When MEMCMD
is set to 1, all burst read accesses
to the transmit buffer are of the
PCI command type Memory
Read Multiple (type 12).
Read accessible always; write
accessible only when either the
STOP or the SPND bit is set.
MEMCMD
is
H_RESET and is not affected by
S_RESET or STOP.
cleared
by
8
EXTREQ
Extended Request. This bit con-
trols the deassertion of REQ for a
burst transaction. If EXTREQ is
set to 0, REQ is deasserted at the
beginning of a burst transaction.
(The
Am79C973/Am79C975
controller never performs more
than one burst transaction within
a single bus mastership period.)
In this mode, the Am79C973/
Am79C975 controller relies on
the PCI latency timer to get
enough bus bandwidth, in case
the system arbiter also removes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C973 | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973KCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975KCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973VCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975VCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C975BKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKC\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKD\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKD\W | 制造商:Advanced Micro Devices 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY 制造商:AMD (Advanced Micro Devices) 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975BKDW | 制造商:Advanced Micro Devices 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY 制造商:AMD (Advanced Micro Devices) 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
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