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參數(shù)資料
| 型號(hào)： | AM79C975 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| 中文描述： | PCnet⑩快速三單芯片10/100 Mbps的PCI以太網(wǎng)控制器集成PHY |
| 文件頁(yè)數(shù)： | 246/304頁(yè) |
| 文件大?。?/td> | 2092K |
| 代理商： | AM79C975 |
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246
Am79C973/Am79C975
P R E L I M I N A R Y
Listed By Group
Note:
OD6 = Open Drain Output, I
OL
= 6 mA, 50 pF
load.
Listed By Function
MCLOCK
SMIU Clock
MCLOCK is the clock pin of the serial management in-
terface. MCLOCK is typically driven by an external
master (e.g., the southbridge or a dedicated microcon-
troller). The Am79C975 controller will drive the clock
line low in order to insert wait states before it starts
sending out data in response to a read. The frequency
of the clock signal can vary between 10 KHz and 100
KHz and it can change from cycle to cycle.
Input/Output
Note:
MCLOCK is capable of running at a frequency
as high as 1.25 MHz to allow for shorter production test
time.
MDATA
SMIU Data
MDATA is the data pin of the serial management inter-
face. MDATA can be driven by an external master (e.g.,
the microcontroller or southbridge) or by the
Am79C975 controller. The interface protocol defines
exactly at what time Am79C975 has to listen to the
MDATA pin and at what time the controller must drive
the pin (see section Basic Operations for more details).
Input/Output
MIRQ
SMIU Interrupt
MIRQ is an asynchronous attention signal that the
Am79C975 controller provides to indicate that a man-
agement frame has been transmitted or received. The
assertion of the MIRQ signal can be controlled by a glo-
bal mask bit (MIRQEN) or individual mask bits
(MRX_DONEM, MTX_DONEM), located in the Com-
Output
mand register. Note that the SMIU interrupt acknowl-
edge does not follow the SMB alert protocol, but simply
requires clearing the interrupt bit.
Basic Operation
Transferring Data
The Serial Management Interface Unit (SMIU) of the
Am79C975 controller uses a two pin interface to com-
municate with other devices. MCLOCK is the clock pin.
MDATA is the data pin. Both signals are bussed and
shared with other devices in the system. There is at
least one master device in the system (e.g., a micro-
controller). A master is a device that initiates a transfer
and also provides the clock signal. The Am79C975
controller is always a slave device.
The master starts a data transfer on the serial manage-
ment bus by asserting the START condition. The
START condition is defined as a HIGH to LOW transi-
tion on MDATA while MCLOCK is HIGH. Data will follow
with the most significant bit (MSB) of a byte transferred
first. Data can only change during the LOW period of
MCLOCK and must be stable on the MDATA pin during
the HIGH period of MCLOCK. Every byte of data must
be acknowledged by the receiving device with the Ac-
knowledge bit (ACK). ACK is defined as a LOW pulse
on MDATA that follows the same timing as a regular
data bit. In a write operation, the Am79C975 controller
is the receiving device and it must generate ACK. In a
read operation, the master is the receiving device and
it must generate ACK. An inverted Acknowledge bit
(NACK) is used to signal the transmitting device that
the data transfer should terminate. A data transfer is
ended when the master asserts the STOP condition.
The STOP condition is defined as a LOW to HIGH tran-
sition on MDATA while MCLOCK is HIGH.
Implementation note: The assertion of START forces
the state machine in the decoder logic to look for the
slave address of the Am79C975 device. The assertion
of STOP forces the state machine to reset and to wait
for the assertion of a START condition.
The first byte in every data transfer is the 7-bit address
of the Am79C975 device followed by the Read/Write
bit. The MSB of the 7-bit address is the first bit on the
MDATA line. A 0 in the Read/Write bit indicates a write
operation from the master to the Am79C975 controller,
a 1 indicates a read operation. The Am79C975 control-
ler does not support the General Call address (00h). It
will ignore the address by not asserting ACK.
Serial Management Interface Unit (SMIU)
Pin
Name
Pin
Function
Type
Driver
No. of
Pins
MCLOCK
SMIU
Clock
I/O
OD6
1
MDATA
SMIU
Data
I/O
OD6
1
MIRQ
SMIU
Interrupt
O
OD6
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C973 | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973KCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975KCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973VCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975VCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C975BKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKC\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKD\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKD\W | 制造商:Advanced Micro Devices 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY 制造商:AMD (Advanced Micro Devices) 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975BKDW | 制造商:Advanced Micro Devices 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY 制造商:AMD (Advanced Micro Devices) 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
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