Am79C973/Am79C975
99
P R E L I M I N A R Y
I
BCR35
I
BCR36
PCI Vendor ID
PCI
Capabilities (PMC) Alias Regis-
ter
PCI DATA Register Zero (DATA0)
Alias Register
PCI DATA Register One (DATA1)
Alias Register
PCI DATA Register Two (DATA2)
Alias Register
PCI
DATA
Register
(DATA3) Alias Register
PCI DATA Register Four (DATA4)
Alias Register
PCI DATA Register Five (DATA5)
Alias Register
PCI DATA Register Six (DATA6)
Alias Register
PCI
DATA
Register
(DATA7) Alias Register
OnNow
Pattern
Register 1
OnNow
Pattern
Register 2
OnNow
Pattern
Register 3
Physical Address Register 0
Physical Address Register 1
Physical Address Register 2
OnNow Miscellaneous
Power
Management
I
BCR37
I
BCR38
I
BCR39
I
BCR40
Three
I
BCR41
I
BCR42
I
BCR43
I
BCR44
Seven
I
BCR45
Matching
I
BCR46
Matching
I
BCR47
Matching
I
CSR12
I
CSR13
I
CSR14
I
CSR116
If PREAD (BCR19, bit 14) and PVALID (BCR19, bit 15)
are cleared to 0, then the EEPROM read has experi-
enced a failure and the contents of the EEPROM pro-
grammable BCR register will be set to default
H_RESET values. The content of the Address PROM
locations, however, will not be cleared.
EEPROM MAP
The automatic EEPROM read operation will access 41
words (i.e., 82 bytes) of the EEPROM. The format of
the EEPROM contents is shown in Table 13 (next
page), beginning with the byte that resides at the low-
est EEPROM address.
Note:
The first bit out of any word location in the EE-
PROM is treated as the MSB of the register being pro-
grammed. For example, the first bit out of EEPROM
word location 09h will be written into BCR4, bit 15; the
second bit out of EEPROM word location 09h will be
written into BCR4, bit 14, etc.
There are two checksum locations within the EE-
PROM. The first checksum will be used by AMD driver
software to verify that the ISO 8802-3 (IEEE/ANSI
802.3) station address has not been corrupted. The
value of bytes 0Ch and 0Dh should match the sum of
bytes 00h through 0Bh and 0Eh and 0Fh. The second
checksum location (byte 51h) is not a checksum total,
but is, instead, a checksum adjustment. The value of
this byte should be such that the total checksum for the
entire 82 bytes of EEPROM data equals the value FFh.
The checksum adjust byte is needed by the
Am79C973/Am79C975 controller in order to verify that
the EEPROM content has not been corrupted.
LED Support
The Am79C973/Am79C975 controller can support up
to four LEDs. LED outputs LED0, LED1, and LED2
allow for direct connection of an LED and its supporting
pullup device.
In applications that want to use the pin to drive an LED
and also have an EEPROM, it might be necessary to
buffer the LED3 circuit from the EEPROM connection.
When an LED circuit is directly connected to the
EEDO/LED3/SRD pin, then it is not possible for most
EEPROM devices to sink enough I
OL
to maintain a valid
low level on the EEDO input to the Am79C973/
Am79C975 controller. Use of buffering can be avoided
if a low power LED is used.
Each LED can be programmed through a BCR register
to indicate one or more of the following network status
or activities: Collision Status, Full-Duplex Link Status,
Half-Duplex Link Status, Receive Match, Receive Sta-
tus, Magic Packet, Disable Transceiver, and Transmit
Status.