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參數(shù)資料
| 型號(hào)： | AM79C976KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 101/309頁 |
| 文件大?。?/td> | 2070K |
| 代理商： | AM79C976KCW |
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8/01/00
Am79C976
101
P R E L I M I N A R Y
The type of wake-up is configured by software using
the bits LCMODE_SW, PMAT_MODE, MPEN_SW and
MPPEN_SW in the CMD7 register. These bits are only
reset by the power-on reset (POR) and are not loaded
from the EEPROM so that they will maintain value
across PCI bus resets and EEPROM read operations.
++$0
The RWU wake-up mechanism is used by systems that
do not have software support for the PCI Bus Power
Management Interface. The wake-up may be config-
ured and controlled completely in hardware, using the
EEPROM to load Am79C976 controller registers and
using the PG pin to enable wake-up. Alternatively, if the
PCI bus power is never removed, wake-up may be con-
figured and enabled by software.
To accommodate systems with hardware that connects
PME to the system power control logic running soft-
ware that is not aware of the PCI Bus Power Manage-
ment Interface, the RWU signal may be routed to the
PME pin by setting the PME_EN_OVR bit (CMD3, bit
4). This is typically set by the EEPROM.
The RWU wake-up is configured by using the bits
LCMODE_EE,
MPEN_EE,
PME_EN_OVR, RWU_POL, RWU_DRIVER and
RWU_GATE in the CMD3 register. These bits are reset
by H_RESET and may be loaded from the EEPROM.
MPPEN_EE,
The Pattern Match wake-up event is not supported by
the RWU wake-up mechanism.
For legacy system support, the Magic Packet wake-up
event may be routed to the INTA pin or to any of the four
LED pins.
(
Link change detect is one of the Wake-up events that is
defined by the OnNow specification and is supported
by the RWU mode. Link Change Detect mode is set
when the LCMODE_EE bit (CMD3, bit 5) is set either
by software or loaded through the EEPROM or when
the LCMODE_SW bit (CMD7, bit 0) is set by software.
When this bit is set, any change in the Link status will
cause the LC_DET bit (STAT0, bit 10) to be set. When
the LC_DET bit is set, the RWU pin will be asserted
and the PME_STATUS bit (PMCSR register, bit 15) will
be set. If either the PME_EN bit (PMCSR, bit 8) or the
PME_EN_OVR bit (CMD3, bit 4) are set, then the PME
signal will also be asserted.
The Am79C976 controller may be configured to enter
link change detect mode immediately upon initial
power-up, regardless of the presence or absence of
PCI bus power. This is accomplished by setting the
LCMODE_EE bit from the EEPROM.
""
A Magic Packet is a frame that is addressed to the
Am79C976 controller and contains a data sequence
made up of 16 consecutive copies of the device
’
s phys-
ical address (PADR[47:0]) anywhere in its data field.
The frame must also cause an address match. By de-
fault, it must be a physical address match, but if the
MPPLBA bit (CMD3, bit 9) is set, logical and broadcast
address matches are also accepted. Regardless of the
setting of MPPLBA, the sequence in the data field of
the frame must be 16 repetitions of the Am79C976 de-
vice
’
s physical address (PADR[47:0]).
Magic Packet mode is enabled by setting the
MPEN_SW bit (CMD7, bit 1) or the MPEN_EE bit
(CMD3, bit 6). Alternatively, Magic Packet mode may
be enabled by setting the MPPEN_SW bit (CMD7, bit
2) or the MPPEN_EE bit (CMD3, bit 8) and deasserting
the PG pin. Magic Packet mode is disabled by clearing
the enable bit(s) or, if only MPPEN_EE and/or
MPPEN_SW are set, by asserting PG.
The Am79C976 controller may be configured to enter
Magic Packet mode immediately upon initial power-up
if PCI bus power is off. This is accomplished by setting
the MPPEN_EE bit from the EEPROM and enabling
Magic Packet mode by the deassertion of PG.
Enabling Magic Packet mode has a similar effect to that
of suspending both transmit and receive. After the
FIFOs have emptied, no frames will be transmitted or
received until Magic Packet mode is disabled.
The WUMI output will be asserted when Magic Packet
mode is enabled.
When the Am79C976 controller detects a Magic
Packet frame, it sets the MP_DET bit (STAT0, bit 11),
the MPINT bit (INT0, bit 13), and the PME_STATUS bit
(PMCSR, bit 15). The RWU pin will also be asserted
and if the PME_EN or the PME_EN_OVR bits are set,
then the PME signal will be asserted as well. If INTREN
(CMD0, bit 1) and MPINTEN (INTEN0, bit 13) are set
to 1, INTA will be asserted. Any one of the four LED
pins can be programmed to indicate that a Magic
Packet frame has been received. MPSE (LED0-3, bit 9)
must be set to 1 to enable that function.
Note:
The polarity of the LED pin can be programmed
to be active HIGH by setting LEDPOL (LED0-3, bit 14)
to 1.
Once a Magic Packet frame is detected, the
Am79C976 controller will discard the frame internally,
but will not resume normal transmit and receive opera-
tions until Magic Packet mode is disabled. Once both of
these events has occurred, indicating that the system
has detected the Magic Packet and is awake, the con-
troller will continue polling receive and transmit de-
scriptor rings where it left off. It is not necessary to
re-initialize the device. If the part is re-initialized, the in-
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C976KD | 制造商:Advanced Micro Devices 功能描述:ETHERNET:MEDIA ACCESS CONTROLLER (MAC) |
| AM79C976KF | 制造商:Advanced Micro Devices 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 208-Pin PQFP 制造商:AMD (Advanced Micro Devices) 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 208-Pin PQFP |
| AM79C976KI | 制造商:Advanced Micro Devices 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 208-Pin PQFP 制造商:AMD (Advanced Micro Devices) 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 208-Pin PQFP |
| AM79C976KIW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller |
| AM79C978 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
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