參數(shù)資料
型號(hào): AM79C976KCW
廠(chǎng)商: ADVANCED MICRO DEVICES INC
元件分類(lèi): 微控制器/微處理器
英文描述: PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller
中文描述: 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP208
封裝: PLASTIC, QFP-208
文件頁(yè)數(shù): 176/309頁(yè)
文件大小: 2070K
代理商: AM79C976KCW
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176
Am79C976
8/01/00
P R E L I M I N A R Y
9
TINTM
Transmit
TINTM is set, the TINT bit will be
masked and unable to set the
INTR bit.
Interrupt
Mask.
If
Read/Write accessible. TINTM is
set by H_RESET but cleared by
S_RESET and is not affected by
STOP.
8
IDONM
Initialization
IDONM is set, the IDON bit will be
masked and unable to set the
INTR bit.
Done
Mask.
If
Read/Write accessible. IDONM is
cleared
by
S_RESET and is not affected by
STOP.
H_RESET
or
7
RES
Reserved location. Read and
written as zeros.
6
DXSUFLO
Obsolete function. Writing has no
effect. Read as undefined.
5
LAPPEN
Look Ahead Packet Processing
Enable. When set to a 1, the
LAPPEN bit will cause the
Am79C976 controller to generate
an interrupt following the descrip-
tor write operation to the first buff-
er of a receive frame. This
interrupt will be generated in ad-
dition to the interrupt that is gen-
erated following the descriptor
write operation to the last buffer
of a receive packet. The interrupt
will be signaled through the RINT
bit of CSR0.
Setting LAPPEN to a 1 also en-
ables the Am79C976 controller to
read the STP bit of receive de-
scriptors. The Am79C976 con-
troller
will
use
information to determine where it
should begin writing a receive
packet
s data. Note that while in
this mode, the Am79C976 con-
troller can write intermediate
packet data to buffers whose de-
scriptors do not contain STP bits
set to 1. Following the write to the
last descriptor used by a packet,
the Am79C976 controller will
scan through the next descriptor
entries to locate the next STP bit
that is set to a 1. The Am79C976
the
STP
controller will begin writing the
next packets data to the buffer
pointed to by that descriptor.
Note that because several de-
scriptors may be allocated by the
host for each packet, and not all
messages may need all of the de-
scriptors that are allocated be-
tween descriptors that contain
STP = 1, then some descriptors/
buffers may be skipped in the
ring. While performing the search
for the next STP bit that is set to
1, the Am79C976 controller will
advance through the receive de-
scriptor ring regardless of the
state of ownership bits. If any of
the entries that are examined
during
this
search
Am79C976 controller ownership
of the descriptor but also indicate
STP = 0, then the Am79C976
controller will reset the OWN bit
to 0 in these entries. If a scanned
entry indicates host ownership
with
STP = 0,
Am79C976 controller will not al-
ter the entry, but will advance to
the next entry.
indicate
then
the
When the STP bit is found to be
true, but the descriptor that con-
tains this setting is not owned by
the Am79C976 controller, then
the Am79C976 controller will stop
advancing through the ring en-
tries and begin periodic polling of
this entry. When the STP bit is
found to be true, and the descrip-
tor that contains this setting is
owned by the Am79C976 control-
ler, then the Am79C976 control-
ler will stop advancing through
the ring entries, store the descrip-
tor information that it has just
read, and wait for the next re-
ceive to arrive.
This behavior allows the host
software to pre-assign buffer
space in such a manner that the
header
portion of a receive pack-
et will always be written to a par-
ticular memory area, and the
data
portion of a receive packet will al-
ways be written to a separate
memory area. The interrupt is
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