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參數(shù)資料
| 型號(hào)： | AT89LP52-20AU |
| 廠商： | Atmel |
| 文件頁(yè)數(shù)： | 107/117頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8051 8K FLASH SPI 44TQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | 89LP |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 36 |
| 程序存儲(chǔ)器容量： | 8KB（8K x 8） |
| 程序存儲(chǔ)器類(lèi)型： | 閃存 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.4 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-TQFP |
| 包裝： | 托盤(pán) |
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9
3709D–MICRO–12/11
AT89LP51/52
2.3.1
Instruction Execution
In Compatibility mode the AT89LP51/52 CPU uses the six-state machine cycle of the standard
8051 where instruction bytes are fetched every three system clock cycles. Execution times in
this mode are identical to AT89S51/52. For greater performance the user can enable Fast mode
by disabling the Compatibility fuse. In Fast mode the CPU fetches one code byte from memory
every clock cycle instead of every three clock cycles. This greatly increases the throughput of
the CPU. Each standard instruction executes in only 1 to 4 clock cycles. See “Instruction Set
Summary” on page 75 for more details. Any software delay loops or instruction-based timing
operations may need to be retuned to achieve the desired results in Fast mode.
2.3.2
System Clock
By default in Compatibility mode the system clock frequency is divided by 2 from the externally
supplied XTAL1 frequency for compatibility with standard 8051s (12 clocks per machine cycle).
The System Clock Divider can scale the system clock versus the oscillator source (See Section
6.4 on page 31). The divide-by-2 can be disabled to operate in X2 mode (6 clocks per machine
cycle) or the clock may be further divided to reduce the operating frequency. In Fast mode the
clock divider defaults to divide by 1.
The system clock source is selectable between the crystal oscillator, an externally driven clock
and an internal 1.8432 MHz auxiliary oscillator. See “System Clock” on page 29 and “User Con-
2.3.3
Reset
The RST pin of the AT89LP51/52 has selectable polarity using the POL pin (formerly EA). When
POL is high the RST pin is active high with a pull-down resistor and when POL is low the RST
pin is active low with a pull-up resistor. For existing AT89S51/52 sockets where EA is tied to
VDD, replacing AT89S51/52 with AT89LP51/52 will maintain the active high reset. Note that
forcing external execution by tying EA low is not supported.
The AT89LP51/52 includes an on-chip Power-On Reset and Brown-out Detector circuit that
ensures that the device is reset from system power up. In most cases a RC startup circuit is not
required on the RST pin, reducing system cost, and the RST pin may be left unconnected if a
board-level reset is not present.
2.3.4
Timer/Counters
A common prescaler is available to divide the time base for Timer 0, Timer 1, Timer 2 and the
WDT. The TPS
3-0 bits in the CLKREG SFR control the prescaler (Table 6-2 on page 31). In
Compatibility mode TPS
3-0 defaults to 0101B, which causes the timers to count once every
machine cycle. The counting rate can be adjusted linearly from the system clock rate to 1/16 of
the system clock rate by changing TPS
3-0. In Fast mode TPS3-0 defaults to 0000B, or the system
clock rate. TPS does not affect Timer 2 in Clock Out or Baud Generator modes.
In Compatibility mode the sampling of the external Timer/Counter pins: T0, T1, T2 and T2EX;
and the external interrupt pins, INT0 and INT1, is also controlled by the prescaler. In Fast mode
these pins are always sampled at the system clock rate.
Both Timer 0 and Timer 1 can toggle their respective counter pins, T0 and T1, when they over-
flow by setting the output enable bits in TCONB.
The Watchdog Timer includes a 7-bit prescaler for longer timeout periods than the AT89S51/52.
Note that in Fast Mode the WDIDLE and DISRTO bits are located in WDTCON and not in
AUXR.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AT89LP52-20JU | 功能描述:8位微控制器 -MCU Single-Cycle 8051 8K ISP Flash MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| AT89LP52-20MU | 功能描述:8位微控制器 -MCU Single-Cycle 8051 8K ISP Flash MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| AT89LP52-20PU | 功能描述:8位微控制器 -MCU Single-Cycle 8051 8K ISP Flash MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| AT89LP6440-20AU | 功能描述:8位微控制器 -MCU Single-Cycle 8051 64K ISP Flash RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| AT89LP6440-20JU | 功能描述:8位微控制器 -MCU Single-Cycle 8051 64K ISP Flash RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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