參數(shù)資料
型號: AT89LP52-20AU
廠商: Atmel
文件頁數(shù): 65/117頁
文件大?。?/td> 0K
描述: IC MCU 8051 8K FLASH SPI 44TQFP
標(biāo)準(zhǔn)包裝: 160
系列: 89LP
核心處理器: 8051
芯體尺寸: 8-位
速度: 20MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
51
3709D–MICRO–12/11
AT89LP51/52
12. Timer 2
The AT89LP51/52 includes a 16-bit Timer/Counter 2 with the following features:
16-bit timer/counter with one 16-bit reload/capture register
One external reload/capture input
Up/Down counting mode with external direction control
UART baud rate generation
Output-pin toggle on timer overflow
Dual slope symmetric operating modes
Timer 2 is included in AT89LP51, unlike AT89S51.
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The
type of operation is selected by bit C/T2 in the SFR T2CON. Timer 2 has three operating modes:
capture, auto-reload (up or down counting), and baud rate generator. The modes are selected
by bits in T2CON and T2MOD, as shown in Table 12-3. Timer 2 also serves as the time base for
the Compare/Capture Array (See Section 13. “External Interrupts” on page 57).
Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the register is incre-
mented every clock cycle. Since a clock cycle consists of one oscillator period, the count rate is
equal to the oscillator frequency. The timer rate can be prescaled by a value between 1 and 16
using the Timer Prescaler (see Table 6-2 on page 31).
In the Counter function, the register is incremented in response to a 1-to-0 transition at its corre-
sponding external input pin, T2. In this function, the external input is sampled every clock cycle.
When the samples show a high in one cycle and a low in the next cycle, the count is incre-
mented. The new count value appears in the register during the cycle following the one in which
the transition was detected. Since two clock cycles are required to recognize a 1-to-0 transition,
the maximum count rate is 1/2 of the oscillator frequency. To ensure that a given level is sam-
pled at least once before it changes, the level should be held for at least one full clock cycle.
The following definitions for Timer 2 are used in the subsequent paragraphs:
Table 12-1.
Timer 2 Operating Modes
RCLK + TCLK
CP/RL2
DCEN
T2OE
TR2
MODE
00
0
1
16-bit Auto-reload
00
1
0
1
16-bit Auto-reload Up-Down
01
X
0
1
16-bit Capture
1
XXX
1
Baud Rate Generator
XX
X
1
Frequency Generator
X
0
(Off)
Table 12-2.
Timer 2 Definitions
Symbol
Definition
MIN
0000H
MAX
FFFFH
BOTTOM
16-bit value of {RCAP2H,RCAP2L}
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