參數(shù)資料
型號: AT89LP52-20AU
廠商: Atmel
文件頁數(shù): 26/117頁
文件大小: 0K
描述: IC MCU 8051 8K FLASH SPI 44TQFP
標(biāo)準(zhǔn)包裝: 160
系列: 89LP
核心處理器: 8051
芯體尺寸: 8-位
速度: 20MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
16
3709D–MICRO–12/11
AT89LP51/52
not accessible while DMEN = 0. FDATA can be accessed only by 16-bit (MOVX @DPTR)
addresses. MOVX @Ri instructions to the FDATA address range will access external memory.
Addresses above the FDATA range are mapped to XDATA.
3.3.2.1
Write Protocol
The FDATA address space accesses an internal nonvolatile data memory. This address space
can be read just like EDATA by issuing a MOVX A,@DPTR; however, writes to FDATA require a
more complex protocol and take several milliseconds to complete.
For internal execution the AT89LP51/52 uses an idle-while-write architecture where the CPU is
placed in an idle state while the write occurs. When the write completes, the CPU will continue
executing with the instruction after the MOVX @DPTR,A instruction that started the write. All
peripherals will continue to function during the write cycle; however, interrupts will not be ser-
viced until the write completes.
For external execution the AT89LP51/52 uses an execute-while-write architecture where the
CPU continues to operate while the write occurs. The software should poll the state of the BUSY
flag to determine when the write completes. Interrupts must be disabled during the write
sequence as the CPU will not be able to vector to the internal interrupt table and care should be
taken that the application does not jump to an internal address until the write completes.
To enable write access to the nonvolatile data memory, the MWEN bit (MEMCON.4) must be set
to one. When MWEN = 1 and DMEN = 1, MOVX @DPTR,A may be used to write to FDATA.
FDATA uses flash memory with a page-based programming model. Flash data memory differs
from traditional EEPROM data memory in the method of writing data. EEPROM generally can
update a single byte with any value. Flash memory splits programming into write and erase
operations. A Flash write can only program zeroes, i.e change ones into zeroes (). Any
ones in the write data are ignored. A Flash erase sets an entire page of data to ones so that all
bytes become FFH. Therefore after an erase, each byte in the page can only be written once
with any possible value. Bytes can be overwritten without an erase as long as only ones are
changed into zeroes. However, if even a single bit needs updating from zero to one (
);
then the contents of the page must first be saved, the entire page must be erased and the zero
bits in all bytes (old and new data combined) must be written. Avoiding unnecessary page
erases greatly improves the endurance of the memory..
The AT89LP51/52 includes 2 data pages of 128 bytes each. One or more bytes in a page may
be written at one time. The AT89LP51/52 includes a temporary page buffer of 64 bytes, or half of
a page. Because the page buffer is 64 bytes long, the maximum number of bytes written at one
time is 64. Therefore, two write cycles are required to fill the entire 128-byte page, one for the
low half page (00H–3FH) and one for the high half page (40H–7FH) as shown in Figure 3-7.
Figure 3-7.
Page Programming Structure
10
01
Low Half Page
00
3F
Data Memory
High Half Page
40
7F
00
3F
Page Buffer
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