參數(shù)資料
型號: AT89LP52-20PU
廠商: Atmel
文件頁數(shù): 31/117頁
文件大?。?/td> 0K
描述: IC MCU 8051 8K FLASH SPI 40PDIP
標準包裝: 10
系列: 89LP
核心處理器: 8051
芯體尺寸: 8-位
速度: 20MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
20
3709D–MICRO–12/11
AT89LP51/52
Notes:
1. AUXR.4 and AUXR.3 function as WDIDLE and DISRTO only in Compatibility mode. In Fast mode these bits are located in
WDTCON.
2. WS1 is only available in Fast mode. WS1 is forced to 0 in Compatibility mode.
Figure 3-12. Fast Mode External Data Memory Write Cycle (WS =00B)
Table 3-3.
AUXR
– Auxiliary Control Register
AUXR = 8EH
Reset Value = xxx0 0000B
Not Bit Addressable
––
WDIDLE(1)
DISRTO(1)
WS1(2)
WS0
EXRAM
DISALE
Bit
7
6
543
21
0
Symbol
Function
WDIDLE
WDT Disable during Idle(1). When WDIDLE = 0 the WDT continues to count in Idle mode. When WDIDLE = 1 the WDT
halts counting in Idle mode.
DISRTO
Disable Reset Output(1). When DISTRO = 0 the reset pin is driven to the same level as POL when the WDT resets.
When DISRTO = 1 the reset pin is input only.
WS[1-0]
Wait State Select. Determines the number of wait states inserted into external memory accesses.
WS1
WS0
Wait States
RD / WR Strobe Width
ALE to RD / WR Setup
000
1 x t
CYC (Fast);
3 x t
CYC (Compatibility)
1 x t
CYC (Fast); 1.5 x tCYC (Compatibility)
011
2 x t
CYC (Fast); 15 x tCYC (Compatibility)
1 x t
CYC (Fast); 1.5 x tCYC (Compatibility)
102
2 x t
CYC (Fast)
2 x t
CYC (Fast)
113
3 x t
CYC (Fast)
2 x t
CYC (Fast)
EXRAM
External RAM Enable. When EXRAM = 0, MOVX instructions can access the internally mapped portions of the address
space. Accesses to addresses above internally mapped memory will access external memory. Set EXRAM = 1 to
bypass the internal memory and map the entire address space to external memory.
DISALE
ALE Disable. When DISALE = 0 the ALE pulse is active at 1/3 of the system clock frequency in Compatibility mode and
1/2 of the system clock frequency in Fast mode. When DISALES = 1 the ALE is inactive (high) unless an external
memory access occurs. DISALE must be set to use P4.4 as a general I/O.
S1
S2
S3
S4
CLK
ALE
WR
DPL or Ri OUT
P0 SFR
P0
P2 SFR
DPH or P2 OUT
P2
DATA OUT
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