參數(shù)資料
型號(hào): AT89LP52-20PU
廠(chǎng)商: Atmel
文件頁(yè)數(shù): 47/117頁(yè)
文件大小: 0K
描述: IC MCU 8051 8K FLASH SPI 40PDIP
標(biāo)準(zhǔn)包裝: 10
系列: 89LP
核心處理器: 8051
芯體尺寸: 8-位
速度: 20MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
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35
3709D–MICRO–12/11
AT89LP51/52
CPU when an interrupt is generated. The timer and UART peripherals continue to function dur-
ing Idle. If these functions are not needed during idle, they should be explicitly disabled by
clearing the appropriate control bits in their respective SFRs. The watchdog may be selectively
enabled or disabled during Idle by setting/clearing the WDIDLE bit. The Brown-out Detector is
always active during Idle. Any enabled interrupt source or reset may terminate Idle mode. When
exiting Idle mode with an interrupt, the interrupt will immediately be serviced, and following RETI
the next instruction to be executed will be the one following the instruction that put the device
into Idle.
The power consumption during Idle mode can be further reduced by prescaling down the system
clock using the System Clock Divider (Section 6.4 on page 31). Be aware that the clock divider
will affect all peripheral functions and baud rates may need to be adjusted to maintain their rate
with the new clock frequency.
.
8.2
Power-down Mode
Setting the Power-down (PD) bit in PCON enters Power-down mode. Power-down mode stops
the oscillator, disables the BOD and powers down the Flash memory in order to minimize power
consumption. Only the power-on circuitry will continue to draw power during Power-down. Dur-
ing Power-down, the power supply voltage may be reduced to the RAM keep-alive voltage. The
RAM contents will be retained, but the SFR contents are not guaranteed once V
DD has been
reduced. Power-down may be exited by external reset, power-on reset, or certain enabled
interrupts.
Table 8-1.
PCON
– Power Control Register
PCON = 87H
Reset Value = 000X 0000B
Not Bit Addressable
SMOD1
SMOD0
PWDEX
POF
GF1
GF0
PD
IDL
Bit
7
6
543
21
0
Symbol
Function
SMOD1
Double Baud Rate bit. Doubles the baud rate of the UART in Modes 1, 2, or 3.
SMOD0
Frame Error Select. When SMOD0 = 1, SCON.7 is SM0. When SMOD0 = 1, SCON.7 is FE. Note that FE will be set after
a frame error regardless of the state of SMOD0.
PWDEX
Power-down Exit Mode. When PWDEX = 0, wake up from Power-down is externally controlled. When PWDEX = 1, wake
up from Power-down is internally timed.
POF
Power Off Flag. POF is set to “1” during power up (i.e. cold reset). It can be set or reset under software control and is not
affected by RST or BOD (i.e. warm resets).
GF1, GF0
General-purpose Flags
PD
Power-down bit. Setting this bit activates power-down operation. The PD bit is cleared automatically by hardware when
waking up from power-down.
IDL
Idle Mode bit. Setting this bit activates Idle mode operation. The IDL bit is cleared automatically by hardware when
waking up from idle
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