參數(shù)資料
型號(hào): AT89LP52-20PU
廠商: Atmel
文件頁數(shù): 45/117頁
文件大小: 0K
描述: IC MCU 8051 8K FLASH SPI 40PDIP
標(biāo)準(zhǔn)包裝: 10
系列: 89LP
核心處理器: 8051
芯體尺寸: 8-位
速度: 20MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
33
3709D–MICRO–12/11
AT89LP51/52
7.2
Brown-out Reset
The AT89LP51/52 has an on-chip Brown-out Detection (BOD) circuit for monitoring the V
DD level
during operation by comparing it to a fixed trigger level. The trigger level V
BOD for the BOD is
nominally 2.0V. The purpose of the BOD is to ensure that if V
DD fails or dips while executing at
speed, the system will gracefully enter reset without the possibility of errors induced by incorrect
execution. A BOD sequence is shown in Figure 7-2. When V
DD decreases to a value below the
trigger level V
BOD, the internal reset is immediately activated. When VDD increases above the
trigger level plus about 200 mV of hysteresis, the start-up timer releases the internal reset after
the specified time-out period has expired (Table 7-1).
Figure 7-2.
Brown-out Detector Reset
The AT89LP51/52 allows for a wide V
DD operating range. The on-chip BOD may not be suffi-
cient to prevent incorrect execution if V
BOD is lower than the minimum required VDD range, such
as when a 5.0V supply is coupled with high frequency operation. In such cases an external
Brown-out Reset circuit connected to the RST pin may be required.
7.3
External Reset
The RST pin of the AT89LP51/52 can function as either an active-low reset input or as an active-
high reset input. The polarity of the RST pin is selectable using the POL pin (formerly EA). When
POL is high the RST pin is active high with an on-chip pull-down resistor tied to GND. When
POL is low the RST pin is active low with an on-chip pull-up resistor tied to V
DD. The RST pin
structure is shown in Figure 7-3. In Compatibility mode the reset pin is sampled every six clock
cycles and must be held active for at least twelve clock cycles to trigger the internal reset. In
Fast mode the reset pin is sampled every clock cycle and must be held active for at least two
clock cycles to trigger the internal reset.
Table 7-1.
Start-up Timer Settings
SUT Fuse 1
SUT Fuse 0
Clock Source
t
SUT (± 5%) s
00
Internal RC/External Clock
16
Crystal Oscillator
1024
01
Internal RC/External Clock
512
Crystal Oscillator
2048
10
Internal RC/External Clock
1024
Crystal Oscillator
4096
11
Internal RC/External Clock
4096
Crystal Oscillator
16384
VDD
Time-out
VPOR
Internal
Reset
tSUT
VBOD
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