參數(shù)資料
型號(hào): ATA5728P6-TKQY
廠商: ATMEL CORP
元件分類: 通信及網(wǎng)絡(luò)
英文描述: SPECIALTY TELECOM CIRCUIT, PDSO20
封裝: SSOP-20
文件頁數(shù): 11/46頁
文件大?。?/td> 776K
代理商: ATA5728P6-TKQY
19
9106E–RKE–07/08
ATA5723/ATA5724/ATA5728
Figure 8-11 “Timing Diagram of the OFF Command using Pin POLLING/_ON” illustrates how to
set the receiver back to polling mode using pin POLLING/_ON. The pin POLLING/_ON must be
held to low for the time period t
on2. After the positive edge on pin POLLING/_ON and the delay
t
on3, the polling mode is active and the sleep time TSleep elapses.
Using the POLLING/_ON command is faster than using pin DATA; however, this requires the
use of an additional connection to the microcontroller.
Figure 8-12 “Activating the Receiving Mode using Pin “POLLING/_ON” illustrates how to set the
receiver to receiving mode using the pin POLLING/_ON. The pin POLLING/_ON must be held to
low. After the delay t
on1, the receiver changes from sleep mode to start-up mode regardless of
the programmed values for T
Sleep and NBit-check. As long as POLLING/_ON is held to low, the val-
ues for T
Sleep and NBit-check is ignored, but not deleted (see Section 10. “Digital Noise
If the receiver is polled exclusively by a microcontroller, T
Sleep must be programmed to 31 (per-
manent sleep mode). In this case the receiver remains in sleep mode as long as POLLING/_ON
is held to high.
9.
Data Clock
The pin DATA_CLK makes a data shift clock available to sample the data stream into a shift reg-
ister. Using this data clock, a microcontroller can easily synchronize the data stream. This clock
can only be used for Manchester and Bi-phase coded signals.
9.1
Generation of the Data Clock
After a successful bit check, the receiver switches from polling mode to receiving mode and the
data stream is available at pin DATA. In receiving mode, the data clock control logic (Man-
chester/Bi-phase demodulator) is active and examines the incoming data stream. This is done,
as with the bit check, by subsequent time frame checks where the distance between two edges
is continuously compared to a programmable time window. As illustrated in Figure 9-1 on page
20, only two distances between two edges in Manchester and Bi-phase coded signals are valid
(T and 2T).
The limits for T are the same as used with the bit check. They can be programmed in the
LIMIT-register (Lim_min and Lim_max, see Table 11-10 on page 28 and Table 11-11 on page
The limits for 2T are calculated as follows:
Lower limit of 2T:
Lim_min_2T = (Lim_min + Lim_max) – (Lim_max – Lim_min)/2
Upper limit of 2T:
Lim_max_2T= (Lim_min + Lim_max) + (Lim_max – Lim_min)/2
(If the result for ’Lim_min_2T’ or ’Lim_max_2T’ is not an integer value, it is rounded up.)
The data clock is available, after the data clock control logic has detected the distance 2T (Start
bit) and is issued with the delay t
Delay after the edge on pin DATA (see Figure 9-1 on page 20).
If the data clock control logic detects a timing or logical error (Manchester code violation), as
illustrated in Figure 9-2 on page 20 and Figure 9-3 on page 21, it stops the output of the data
clock. The receiver remains in receiving mode and starts with the bit check. If the bit check was
successful and the start bit has been detected, the data clock control logic starts again with the
generation of the data clock (see Figure 9-4 on page 21).
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