參數(shù)資料
型號(hào)： ATA5728P6-TKQY
廠商： ATMEL CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, PDSO20
封裝： SSOP-20
文件頁(yè)數(shù)： 13/46頁(yè)
文件大小： 776K
代理商： ATA5728P6-TKQY
20
9106E–RKE–07/08
ATA5723/ATA5724/ATA5728
Use the function of the data clock only in conjunction with the bit check 3, 6 or 9 is recom-
mended. If the bit check is set to 0 or the receiver is set to receiving mode using the pin
POLLING/_ON, the data clock is available if the data clock control logic has detected the dis-
tance 2T (Start bit).
Note that for Bi-phase-coded signals, the data clock is issued at the end of the bit.
Figure 9-1.
Timing Diagram of the Data Clock
Figure 9-2.
Data Clock Disappears Because of a Timing Error
Data_out (DATA)
DATA_CLK
Dem_out
t
Delay
'1'
'0'
'1'
'0'
'1'
2T
Data
Preburst
Start bit
Bit-check mode
Receiving mode,
data clock control logic active
Bit check ok
T
'1'
t
P_Data_Clk
Data_out (DATA)
DATA_CLK
Dem_out
T
ee
Tee < TLim_min or TLim_max < Tee < TLim_min_2T or Tee > TLim_max_2T
'1'
'0'
'1'
'0'
'1'
Data
Receiving mode,
data clock control
logic active
Receiving mode,
bit check active
Timing error
'1'
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