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參數(shù)資料
| 型號： | ATA5728P6-TKQY |
| 廠商： | ATMEL CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PDSO20 |
| 封裝： | SSOP-20 |
| 文件頁數(shù)： | 2/46頁 |
| 文件大?。?/td> | 776K |
| 代理商： | ATA5728P6-TKQY |
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10
9106E–RKE–07/08
ATA5723/ATA5724/ATA5728
6.
Polling Circuit and Control Logic
The receiver is designed to consume less than 1 mA while being sensitive to signals from a cor-
responding transmitter. This is achieved using the polling circuit. This circuit enables the signal
path periodically for a short time. During this time the bit-check logic verifies the presence of a
valid transmitter signal. Only if a valid signal is detected, the receiver remains active and trans-
fers the data to the connected microcontroller. If there is no valid signal present, the receiver is
in sleep mode most of the time resulting in low current consumption. This condition is called poll-
ing mode. A connected microcontroller is disabled during that time.
All relevant parameters of the polling logic can be configured by the connected microcontroller.
This flexibility enables the user to meet the specifications in terms of current consumption, sys-
tem response time, data rate etc.
The receiver is very flexible with regards to the number of connection wires to the microcon-
troller. It can be either operated by a single bi-directional line to save ports to the connected
microcontroller or it can be operated by up to five uni-directional ports.
7.
Basic Clock Cycle of the Digital Circuitry
The complete timing of the digital circuitry and the analog filtering is derived from one clock. This
clock cycle T
Clk is derived from the crystal oscillator (XTO) in combination with a divide by 28 or
30 circuit. According to Section 3. “RF Front-end” on page 5, the frequency of the crystal oscilla-
tor (f
XTO) is defined by the RF input signal (fRFin) which also defines the operating frequency of
the local oscillator (f
LO). The basic clock cycle for ATA5724 and ATA5728 is TClk 28/fXTO giving
T
Clk = 2.066 s for fRF = 868.3 MHz and TClk = 2.069 s for fRF = 433.92 MHz. For ATA5723 the
basic clock cycle is T
Clk =30/fREF giving TClk = 2.0382 s for fRF =315 MHz.
T
Clk controls the following application-relevant parameters:
Timing of the polling circuit including bit check
Timing of the analog and digital signal processing
Timing of the register programming
Frequency of the reset marker
IF filter center frequency (fIF0)
Most applications are dominated by three transmission frequencies: f
Transmit = 315 MHz is mainly
used in USA, f
Transmit = 868.3 MHz and 433.92 MHz in Europe. All timings are based on TClk. For
the aforementioned frequencies, T
Clk is given as:
Application 315 MHz band (f
XTO = 14.71875 MHz, fLO = 314.13 MHz, TClk = 2.0382 s)
Application 868.3 MHz band (f
XTO = 13.55234 MHz, fLO = 867.35 MHz, TClk = 2.066 s)
Application 433.92 MHz band (f
XTO = 13.52875 MHz, fLO = 432.93 MHz, TClk = 2.0696 s)
For calculation of T
Clk for applications using other frequency bands, see table in Section 18.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ATA5743 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:UHF ASK/FSK Receiver |
| ATA5743P3-TGQY | 功能描述:射頻接收器 ASK/FSK Rec.(imp.FSK sensitiv IF=300kH) RoHS:否 制造商:Skyworks Solutions, Inc. 類型:GPS Receiver 封裝 / 箱體:QFN-24 工作頻率:4.092 MHz 工作電源電壓:3.3 V 封裝:Reel |
| ATA5743P3-TGQY 19 | 制造商:Atmel Corporation 功能描述:ASK/FSK Rec.(impr.FSK sensitiv,IF=300kH) |
| ATA5743P3-TGQY 19 | 功能描述:射頻接收器 ASK/FSK Rec(impr.FSK SensitivIF=300kH) RoHS:否 制造商:Skyworks Solutions, Inc. 類型:GPS Receiver 封裝 / 箱體:QFN-24 工作頻率:4.092 MHz 工作電源電壓:3.3 V 封裝:Reel |
| ATA5743P3-TGSY | 功能描述:射頻接收器 ASK/FSK Rec.(imp.FSK sensitiv IF=300kH) RoHS:否 制造商:Skyworks Solutions, Inc. 類型:GPS Receiver 封裝 / 箱體:QFN-24 工作頻率:4.092 MHz 工作電源電壓:3.3 V 封裝:Reel |
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