參數(shù)資料
型號: ATA5728P6-TKQY
廠商: ATMEL CORP
元件分類: 通信及網(wǎng)絡(luò)
英文描述: SPECIALTY TELECOM CIRCUIT, PDSO20
封裝: SSOP-20
文件頁數(shù): 8/46頁
文件大?。?/td> 776K
代理商: ATA5728P6-TKQY
16
9106E–RKE–07/08
ATA5723/ATA5724/ATA5728
8.6
Digital Signal Processing
The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different ways and
as a result converted into the output signal data. This processing depends on the selected
baud-rate range (BR_Range). Figure 8-7 illustrates how Dem_out is synchronized by the
extended clock cycle T
XClk. This clock is also used for the bit-check counter. Data can change its
state only after T
XClk has elapsed. The edge-to-edge time period tee of the Data signal as a result
is always an integral multiple of T
XClk.
The minimum time period between two edges of the data signal is limited to t
ee ≥ TDATA_min. This
implies an efficient suppression of spikes at the DATA output. At the same time it limits the max-
imum frequency of edges at DATA. This eases the interrupt handling of a connected
microcontroller.
The maximum time period for DATA to stay low is limited to T
DATA_L_max. This function is
employed to ensure a finite response time in programming or switching off the receiver via pin
DATA. T
DATA_L_max is therefore longer than the maximum time period indicated by the transmitter
data stream. Figure 8-9 on page 17 gives an example where Dem_out remains Low after the
receiver has switched to receiving mode.
Figure 8-7.
Synchronization of the Demodulator Output
Figure 8-8.
Debouncing of the Demodulator Output
Data_out (DATA)
Clock bit-check
counter
Dem_out
T
XClk
t
ee
Data_out (DATA)
Dem_out
t
ee
t
ee
t
ee
t
DATA_min
t
DATA_min
t
DATA_min
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