參數(shù)資料
型號: ATA5728P6-TKQY
廠商: ATMEL CORP
元件分類: 通信及網(wǎng)絡(luò)
英文描述: SPECIALTY TELECOM CIRCUIT, PDSO20
封裝: SSOP-20
文件頁數(shù): 9/46頁
文件大小: 776K
代理商: ATA5728P6-TKQY
17
9106E–RKE–07/08
ATA5723/ATA5724/ATA5728
Figure 8-9.
Steady L State Limited DATA Output Pattern After Transmission
After the end of a data transmission, the receiver remains active. Depending of the bit
Noise_Disable in the OPMODE register, the output signal at pin DATA is high or random noise
pulses appear at pin DATA (see Section 10. “Digital Noise Suppression” on page 23). The
edge-to-edge time period t
ee of the majority of these noise pulses is equal or slightly higher than
T
DATA_min.
8.7
Switching the Receiver Back to Sleep Mode
The receiver can be set back to polling mode via pin DATA or via pin POLLING/_ON.
When using pin DATA, this pin must be pulled to low by the connected microcontroller for the
period t1. Figure 8-10 on page 18 illustrates the timing of the OFF command (see Figure 13-2 on
page 30). The minimum value of t1 depends on the BR_Range. The maximum value for t1 is not
limited; however, exceeding the specified value to prevent erasing the reset marker is not rec-
ommended. Note also that an internal reset for the OPMODE and the LIMIT register is
generated if t1 exceeds the specified values. This item is explained in more detail in the Section
11. “Configuring the Receiver” on page 25. Setting the receiver to sleep mode via DATA is
achieved by programming bit 1 to “1” during the register configuration. Only one sync pulse (t3)
is issued.
The duration of the OFF command is determined by the sum of t1, t2, and t10. The sleep time
T
Sleep elapses after the OFF command. Note that the capacitive load at pin DATA is limited (see
IC_ACTIVE
Data_out (DATA)
Dem_out
Bit check
t
DATA_L_max
t
DATA_min
Receiving mode
Start-up mode
Bit-check mode
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