參數(shù)資料
型號(hào)： ATA5728P6-TKQY
廠商： ATMEL CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, PDSO20
封裝： SSOP-20
文件頁(yè)數(shù)： 14/46頁(yè)
文件大?。?/td> 776K
代理商： ATA5728P6-TKQY
21
9106E–RKE–07/08
ATA5723/ATA5724/ATA5728
Figure 9-3.
Data Clock Disappears Because of a Logical Error
Figure 9-4.
Output of the Data Clock After a Successful Bit Check
The delay of the data clock is calculated as follows: t
Delay = tDelay1 + tDelay2
t
Delay1 is the delay between the internal signals Data_Out and Data_In. For the rising edge, tDelay1
depends on the capacitive load C
L at pin DATA and the external pull-up resistor Rpup. For the
falling edge, t
Delay1 depends additionally on the external voltage VX (see Figure 9-5, Figure 9-6
on page 22 and Figure 13-2 on page 30). When the level of Data_In is equal to the level of
Data_Out, the data clock is issued after an additional delay t
Delay2.
Note that the capacitive load at pin DATA is limited. If the maximum tolerated capacitive load at
pin DATA is exceeded, the data clock disappears (see Section 14. “Data Interface” on page 32).
Data_out (DATA)
DATA_CLK
Dem_out
'1'
'0'
'1'
'0'
'1'
'?'
Data
Receiving mode,
data clock control
logic active
Receiving mode,
bit check active
Logical error (Manchester code violation)
'0'
'1'
Data_out (DATA)
DATA_CLK
Dem_out
'1'
'0'
'1'
'0'
'1'
Data
Bit check ok
Start bit
Receiving mode,
data clock control
logic active
Receiving mode,
bit check active
'1'
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