參數(shù)資料
型號: ATA5728P6-TKQY
廠商: ATMEL CORP
元件分類: 通信及網(wǎng)絡(luò)
英文描述: SPECIALTY TELECOM CIRCUIT, PDSO20
封裝: SSOP-20
文件頁數(shù): 22/46頁
文件大?。?/td> 776K
代理商: ATA5728P6-TKQY
29
9106E–RKE–07/08
ATA5723/ATA5724/ATA5728
12. Conservation of the Register Information
The ATA5723/ATA5724 uses an integrated power-on reset and brown-out detection circuitry as
a mechanism to preserve the RAM register information.
According to Figure 12-1, a power-on reset (POR) is generated if the supply voltage V
S drops
below the threshold voltage V
ThReset. The default parameters are programmed into the configura-
tion registers in that condition. The POR is cancelled after the minimum reset period t
Rst when VS
exceeds V
ThReset. A POR is also generated when the supply voltage of the receiver is turned on.
To indicate that condition, the receiver displays a reset marker (RM) at pin DATA after a reset.
The RM is represented by the fixed frequency f
RM at a 50% duty-cycle. RM can be cancelled
using a low pulse t1 at pin DATA. The RM has the following characteristics:
f
RM is lower than the lowest feasible frequency of a data signal. Due to this, RM cannot be
misinterpreted by the connected microcontroller.
If the receiver is set back to polling mode using pin DATA, RM cannot be cancelled
accidentally if t1 is applied as described in the proposal in Section 13. “Programming the
Using this conservation mechanism, the receiver cannot lose its register information without
communicating this condition using the reset marker RM.
Figure 12-1. Generation of the Power-on Reset
POR
Data_out (DATA)
X
t
Rst
V
Threset
V
S
1/f
RM
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