參數(shù)資料
型號: ATAM893T-TKS
廠商: Atmel
文件頁數(shù): 29/98頁
文件大小: 0K
描述: IC MON TIRE-PRESS ATARX9X SER
標(biāo)準(zhǔn)包裝: 830
系列: MARC4
核心處理器: MARC4
芯體尺寸: 4-位
速度: 4MHz
連通性: SSI(2 線,3 線)
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 4KB(4K x 8)
程序存儲器類型: EEPROM
EEPROM 大小: 64 x 16
RAM 容量: 256 x 4
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 6.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 20-SOIC(0.209",5.30mm 寬)
包裝: 管件
35
4680C–4BMCU–01/05
ATAM893-D
5.3.1.2
Timer 1 Control Register 2 (T1C2)
Bit 3 = MSB, Bit 0 = LSB
5.3.1.3
Watchdog Control Register (WDC)
Bit 3 = MSB, Bit 0 = LSB
Both these bits control the time interval for the watchdog reset.
Address: ’7’hex - Subaddress: ’9’hex
Bit 3
Bit 2
Bit 1
Bit 0
T1C2
T1BP
T1CS
T1IM
Reset value: x111b
T1BP
Timer 1 SUBCL ByPassed
T1BP = 1, TIOUT = T1MUX
T1BP = 0, T1OUT = SUBCL
T1CS
Timer 1 input Clock Select
T1CS = 1, CL1 = SUBCL (see Figure 5-8 on page 33)
T1CS = 0, CL1 = SYSCL (see Figure 5-8 on page 33)
T1IM
Timer 1 Interrupt Mask
T1IM = 1, disables Timer 1 interrupt
T1IM = 0, enables Timer 1 interrupt
Address: ’7’hex - Subaddress: ’A’hex
Bit 3
Bit 2
Bit 1
Bit 0
WDC
WDL
WDR
WDT1
WDT0
Reset value: 1111b
WDL
WatchDog Lock mode
WDL = 1, the watchdog can be enabled and disabled by using the WDR-bit
WDL = 0, the watchdog is enabled and locked. In this mode the WDR-bit has no
effect. After the WDL-bit is cleared, the watchdog is active until a system
reset or power-on reset occurs.
WDR
WatchDog Run and stop mode
WDR = 1, the watchdog is stopped/disabled
WDR = 0, the watchdog is active/enabled
WDT1
WatchDog Time 1
WDT0
WatchDog Time 0
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