參數(shù)資料
型號: ATAM893T-TKS
廠商: Atmel
文件頁數(shù): 86/98頁
文件大?。?/td> 0K
描述: IC MON TIRE-PRESS ATARX9X SER
標(biāo)準(zhǔn)包裝: 830
系列: MARC4
核心處理器: MARC4
芯體尺寸: 4-位
速度: 4MHz
連通性: SSI(2 線,3 線)
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲(chǔ)器容量: 4KB(4K x 8)
程序存儲(chǔ)器類型: EEPROM
EEPROM 大小: 64 x 16
RAM 容量: 256 x 4
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 6.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 20-SOIC(0.209",5.30mm 寬)
包裝: 管件
87
4680C–4BMCU–01/05
ATAM893-D
6.2.2.2
Write One Data Byte
6.2.2.3
Write Two Data Bytes
6.2.2.4
Write Control Byte Only
6.2.2.5
Write Control Bytes
A
→acknowledge; HB: high byte; LB: low byte; R: row address
6.2.3
Read Operations
The EEPROM allows byte-, word- and current address read operations. The read operations are
initiated in the same way as write operations. Every read access is initiated by sending the
START condition followed by the control byte which contains the address and the read mode.
When the device has received a read command, it returns an acknowledge, loads the addressed
word into the read/write buffer and sends the selected data byte to the master. The master has
to acknowledge the received byte if it wants to proceed with the read operation. If two bytes are
read out from the buffer the device increments respectively decrements the word address auto-
matically and loads the buffer with the next word. The read mode bits determines if the low or
high byte is read first from the buffer and if the word address is incremented or decremented for
the next read access. If the memory address limit is reached, the data word address will “roll
over” and the sequential read will continue. The master can terminate the read operation after
every byte by not responding with an acknowledge (N) by issuing a stop condition.
Start
Control byte
A
Data byte 1
A
Stop
Start
Control byte
A
Data byte 1
A
Data byte 2
A
Stop
Start
Control byte
A
Stop
MSB
LSB
Write low byte first
A4
A3
A2
A1
A0
C1
C0
R/NW
Row address
0
1
0
Byte order
LB(R)
HB(R)
MSB
LSB
Write high byte first
A4
A3
A2
A1
A0
C1
C0
R/NW
Row address
1
0
Byte order
HB(R)
LB(R)
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