參數(shù)資料
型號: ATAM893T-TKS
廠商: Atmel
文件頁數(shù): 34/98頁
文件大小: 0K
描述: IC MON TIRE-PRESS ATARX9X SER
標(biāo)準(zhǔn)包裝: 830
系列: MARC4
核心處理器: MARC4
芯體尺寸: 4-位
速度: 4MHz
連通性: SSI(2 線,3 線)
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 4KB(4K x 8)
程序存儲器類型: EEPROM
EEPROM 大?。?/td> 64 x 16
RAM 容量: 256 x 4
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 6.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 20-SOIC(0.209",5.30mm 寬)
包裝: 管件
4
4680C–4BMCU–01/05
ATAM893-D
3.5
RC-oscillator Frequency
The typical frequency of the internal RC-oscillator is about 5% higher for the Flash part com-
pared to the ROM part. But due to the wide range of ±50% overall tolerances this should not
affect the application too much.
This 5% is also valid for the RC-oscillator with an external resistor. For a frequency of 4 MHz the
flash part requires a resistor of 180 k, while the ROM part only needs 170 k.
3.6
High Drive Outputs
On request the ROM parts offer a high current output selection. These pins than are twice as
strong as in the standard configuration. The ATAM893-D does not offer this selection. Only the
Timer 2 output (BP42) and the Timer 3 output (BP60) are configured as high current outputs for
the low side driver by default. This configuration is fixed and cannot be changed by the
customer.
4.
MARC4 Architecture
4.1
General Description
The MARC4 microcontroller consists of an advanced stack-based, 4-bit CPU core and on-chip
peripherals. The CPU is based on the Harvard architecture with physically separate program
memory (ROM) and data memory (RAM). Three independent buses, the instruction bus, the
memory bus and the I/O bus, are used for parallel communication between ROM, RAM and
peripherals. This enhances program execution speed by allowing both instruction prefetching,
and a simultaneous communication to the on-chip peripheral circuitry. The extremely powerful
integrated interrupt controller with associated eight prioritized interrupt levels supports fast and
efficient processing of hardware events. The MARC4 is designed for the high-level programming
language qFORTH. The core includes both, an expression and a return stack. This architecture
enables high-level language programming without any loss of efficiency or code density.
Figure 4-1.
MARC4 Core
Instruction
decoder
CCR
TOS
ALU
RAM
RP
X
Y
Program
256 x 4-bit
MARC4 CORE
Clock
Reset
Sleep
Memory bus
I/O bus
Instruction
bus
Reset
System
clock
Interrupt
controller
On-chip peripheral modules
memory
SP
PC
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