參數(shù)資料
型號(hào): ATAM893T-TKS
廠商: Atmel
文件頁數(shù): 55/98頁
文件大小: 0K
描述: IC MON TIRE-PRESS ATARX9X SER
標(biāo)準(zhǔn)包裝: 830
系列: MARC4
核心處理器: MARC4
芯體尺寸: 4-位
速度: 4MHz
連通性: SSI(2 線,3 線)
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲(chǔ)器容量: 4KB(4K x 8)
程序存儲(chǔ)器類型: EEPROM
EEPROM 大?。?/td> 64 x 16
RAM 容量: 256 x 4
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 6.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 20-SOIC(0.209",5.30mm 寬)
包裝: 管件
59
4680C–4BMCU–01/05
ATAM893-D
5.3.3.13
Timer 3 Compare Mode Register 2 (T3CM2)
T3CM2 contains the mask bits for the match event of Counter 3 compare register 2
The compare registers and corresponding counter reset masks can be used to program the
counter time intervals and the toggle masks can be used to program the output signal. The sin-
gle-action mask can also be used in this mode. It starts operating after the timer started with
T3R.
5.3.3.14
Timer 3 COmpare Register 1 (T3CO1) Byte Write
5.3.3.15
Timer 3 COmpare Register 2 (T3CO2) Byte Write
Address: 'B'hex — Subaddress: '3'hex
Bit 3Bit 2Bit 1Bit 0
T3CM2
T3SM2
T3TM2
T3RM2
T3IM2
Reset value: 0000b
T3SM2
Timer 3 Single action Mask bit 2
T3SM2 = 0, disables single-action compare mode
T3SM2 = 1, enables single-compare mode. After this bit is set, the compare
register (T3CO2) is used until the next compare match
T3TM2
Timer 3 compare Toggle action Mask bit 2
T3TM2 = 0, disables compare toggle
T3TM2 = 1, enables compare toggle. A match of Counter 3 with the compare
register (T3CO2) toggles the output flip-flop (TOG3)
T3RM2
Timer 3 Reset Mask bit 2
T3RM2 = 0, disables counter reset
T3RM2 = 1, enables counter reset. A match of Counter 3 with the compare
register (T3CO2) resets the Counter 3
T3IM2
Timer 3 Interrupt Mask bit 2
T3RM2 = 0, disables Timer 3 interrupt for T3CO2 register
T3RM2 = 1, enables Timer 3 interrupt for T3CO2 register
Address: 'B'hex — Subaddress: '4'hex
High Nibble
Second write cycle
Bit 7
Bit 6
Bit 5
Bit 4
Reset value: 1111b
Low Nibble
First write cycle
Bit 3
Bit 2
Bit 1
Bit 0
Reset value: 1111b
Address: 'Beaux — Subaddress: '5'hex
High Nibble
Second write cycle
Bit 7
Bit 6
Bit 5
Bit 4
Reset value: 1111b
Low Nibble
First write cycle
Bit 3
Bit 2
Bit 1
Bit 0
Reset value: 1111b
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