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參數(shù)資料
| 型號： | CP2120-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 3/24頁 |
| 文件大小： | 0K |
| 描述： | IC I/O EXPANDER I2C/SPI 8B 20QFN |
| 產(chǎn)品培訓(xùn)模塊： | CP21xx USB Bridge |
| 標(biāo)準(zhǔn)包裝： | 91 |
| 接口： | I²C，SPI |
| 輸入/輸出數(shù)： | 8 |
| 中斷輸出： | 是 |
| 頻率 - 時鐘： | 400kHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-QFN（4x4） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 627 (CN2011-ZH PDF) |
| 其它名稱： | 336-1324 |
CP2120
Rev. 0.4
11
5.2.2. Read From Internal Register
A Read from Internal Register command retrieves the current value of one of the CP2120's internal registers. The
command begins with the command byte, 0x21, followed by the internal register address. This byte is followed by
the transmission of a "don't care" byte, which can be of any value and is ignored by the CP2120. After the "don't
care" byte, the internal register value is transmitted across the MISO line.
5.3. SPI Byte Orientation
The SPI Configuration command configures the bit orientation of transfers across the SPI bus to one of two states.
If SPI transmits most-significant-bit first, bit 7 is transmitted first. If SPI transmits least-significant-bit first, bit 0 is
transmitted first.
5.3.1. SPI Configuration
The command begins with the command byte (0x18), followed by SPI Configuration byte, which should equal one
of the values shown in the following table. Any values other than those listed in the table are ignored.
5.4. SPI Timing Diagrams
Figure 4. SPI Slave Timing
Byte Value
Configuration
0x81
Most Significant Bit First
0x42
Least Significant Bit First
COMMAND
0x21
REGISTER
Address
Don’t Care
SPI Master
CP2120
REGISTER
DATA
COMMAND
0x18
SPI
CONFIGURATION
SPI Master
NSS
SCK*
MOSI
MISO
TSEZ
TSOH
TSIH
TSIS
TCKH
TSE
TCKL
TSD
TSLH
TSDZ
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