5.5. I2C Activity During SPI Transactions If" />
參數(shù)資料
型號: CP2120-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 4/24頁
文件大小: 0K
描述: IC I/O EXPANDER I2C/SPI 8B 20QFN
產(chǎn)品培訓(xùn)模塊: CP21xx USB Bridge
標準包裝: 91
接口: I²C,SPI
輸入/輸出數(shù): 8
中斷輸出:
頻率 - 時鐘: 400kHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 20-QFN(4x4)
包裝: 管件
產(chǎn)品目錄頁面: 627 (CN2011-ZH PDF)
其它名稱: 336-1324
CP2120
12
Rev. 0.4
5.5. I2C Activity During SPI Transactions
If the SPI Master attempts to transmit a command to the CP2120 while the I2C bus is inactive, the CP2120 will
disable its slave response. If an I2C Master device on the bus attempts to address the CP2120 during this time, the
CP2120 will not ACK the address defined in the I2CADR Internal Register.
If the SPI Master attempts to transmit a command to the CP2120 while the CP2120 is acting as the Master on the
I2C bus, the CP2120 will suspend I2C bus activity until the SPI Master has completed transmission of the
command. For instance, if the SPI Master calls the Read Internal Register command while the CP2120 is in the
middle of an I2C transaction, that I2C transaction will stall until the CP2120 completely processes the Read Internal
Register command.
Table 4. SPI Slave Timing Parameters
Slave Mode Timing* (See Figure 4)
TSE
NSS Falling to First SCLK Edge
2xTSYSCLK
—ns
TSD
Last SCLK Edge to NSS Rising
2xTSYSCLK
—ns
TSEZ
NSS Falling to MISO Valid
—4 x TSYSCLK
ns
TSDZ
NSS Rising to MISO High-Z
—4 x TSYSCLK
ns
TCKH
SCLK High Time
5xTSYSCLK
—ns
TCKL
SCLK Low Time
5xTSYSCLK
—ns
TSIS
MOSI Valid to SCLK Sample Edge
2xTSYSCLK
—ns
TSIH
SCLK Sample Edge to MOSI Change
2xTSYSCLK
—ns
TSOH
SCLK Shift Edge to MISO Change
—4 x TSYSCLK
ns
TSLH
Last SCLK Edge to MISO Change
(CKPHA = 1 ONLY)
6xTSYSCLK
8xTSYSCLK
ns
*Note: TSYSCLK equals 24.5 MHz.
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