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參數(shù)資料
| 型號： | CP2120-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC I/O EXPANDER I2C/SPI 8B 20QFN |
| 產(chǎn)品培訓(xùn)模塊： | CP21xx USB Bridge |
| 標(biāo)準(zhǔn)包裝： | 91 |
| 接口： | I²C，SPI |
| 輸入/輸出數(shù)： | 8 |
| 中斷輸出： | 是 |
| 頻率 - 時鐘： | 400kHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-QFN（4x4） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 627 (CN2011-ZH PDF) |
| 其它名稱： | 336-1324 |
CP2120
Rev. 0.4
15
The SPI2I2C provides additional SMBus-related timers to enable I2C protocol compatibility. Setting the I2C Bus
Free Detect enables the device to poll the SMBus lines and determine when a transfer can begin. Setting the SCL
Low Time Out detect will cause an SMBus transaction to abort if the SCL line has been held low by a device for a
period of approximately 25 ms.
Internal Register Definition 4. I2CTO2: Additional I2C Time Outs
6.3. I2C Status
The CP2120 maintains an Internal Register, I2CSTAT, which describes the current status of the I2C Interface. The
I2CSTAT register can be read at any time. The CP2120 updates I2CSTAT when an I2C transaction begins, when
an I2C transaction completes (successfully or unsuccessfully), and when a received SPI command contains errors.
It is not recommended that an SPI master poll the CP2120's I2CSTAT Internal Register to determine when an I2C
transaction has completed. The SPI master should instead watch for the INT pin to drop low, and then read the
I2CSTAT register to determine the I2C transaction results.
Internal Register Address:
0x09
Reset Value:
0x00
Bit 1:
I2C Bus Free Detect
0: Bus Free Detect Disabled
1: Bus Free Detect Enabled
Bit 0:
I2C SCL Low Time Out Detect
0: SCL Low Time Out Detect disable
1: SCL Low Time Out Detect enable
R/W
Reserved
FREN
LWEN
Bit 7Bit 6Bit 5Bit 4
Bit3
Bit 2Bit 1Bit 0
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