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參數(shù)資料
| 型號： | CP2120-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC I/O EXPANDER I2C/SPI 8B 20QFN |
| 產(chǎn)品培訓(xùn)模塊： | CP21xx USB Bridge |
| 標(biāo)準(zhǔn)包裝： | 91 |
| 接口： | I²C，SPI |
| 輸入/輸出數(shù)： | 8 |
| 中斷輸出： | 是 |
| 頻率 - 時鐘： | 400kHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-QFN（4x4） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 627 (CN2011-ZH PDF) |
| 其它名稱： | 336-1324 |
CP2120
Rev. 0.4
13
6. I2C Serial Interface
The CP2120 provides an I2C interface able to transfer data at frequencies up to 400 kHz. During a transaction, the
CP2120, operating as the I2C master, sources a data clock on the SCL pin as data travels across the bidirectional
SDA pin to and from an I2C slave device. The I2C interface lines each require a pull-up resistor. Figure 5 shows a
typical I2C bus.
Figure 5. Typical I2C Bus*
*Note: VDD is defined in Table 1, “Absolute Maximum Ratings,” on page 4. For Rpu values, please see “6.1.
6.1. Determining Pull-Up Register Values
Logic low to logic high transitions on the SCL and SDA pins, which are configured to open-drain output with
external pull-ups to VDD, take the form of an exponential curve with an RC time constant, where C equals the
capacitance of the bus and R equals the pull-up resistor value. I2C specification defines rise time as the time
required for a signal level to change from Vmin +0.15 V to Vmax-0.15 V. By solving the exponential equation using
a Vmin of 0 V and a Vmax of 3.3 V, the following equation can be used to find values for pull-up resistors:
Rise time = 3.04448 RC
Bus capacitance is governed by a number of factors, including signal trace length and capacitance introduced by
devices on the bus. 8 mm PCB signal traces on a two-layer board generally add 1 pF of capacitance per
centimeter of trace length. To determine the amount of capacitance introduced to the bus by I2C devices, consult
those devices’ datasheets. The maximum capacitance allowed before the bus violates I2C specification is 400 pF.
Rise time requirements vary depending on each connected I2C device’s timing requirements and the SCL clock
frequency. The maximum rise time allowed by the I2C specification is 1000 ns.
6.2. I2C Internal Registers
Features of the I2C interface are configured through the CP2120's Internal Registers. SCL clock frequency is set
by writing to the I2CCLK Internal Register. The frequency can be determined using the equation below. The I2C
frequency configured by the I2CCLOCK register is only an approximate frequency. Actual I2C frequencies can vary
due to conditions on the bus, such as a slave device extending the SCL low time.
Equation 1. I2C Clock Frequency
IC-BUS Device
CP2120
IC-BUS DEVICE
VDD
RpU
IC-bus
SDA
SCL
I
2
C Clock Frequency (kHz)
2000
I
2
CCLK
---------------------
=
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