參數(shù)資料
型號: CP2201EK
廠商: Silicon Laboratories Inc
文件頁數(shù): 105/108頁
文件大小: 0K
描述: KIT EVAL FOR CP2201 ETH CTRLR
標準包裝: 1
主要目的: 接口,以太網(wǎng)傳感器
嵌入式: 是,MCU,8 位
已用 IC / 零件: CP2200,CP2201
主要屬性: 溫度和光傳感器
次要屬性: 圖形用戶界面
已供物品: 板,電源,線纜,CD
產(chǎn)品目錄頁面: 627 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: 336-1313-ND - IC ETH CTRLR SNGL-CHIP 28QFN
336-1312-ND - IC ETH CTRLR SNGL-CHIP 48TQFP
其它名稱: 336-1316
CP2200/1
96
Rev. 1.0
16. Parallel Interface
The CP2200/1 has an 8-bit parallel host interface used to access the direct registers on the device. The parallel
interface supports multiplexed or non-multiplexed operation using the Intel or Motorola bus format. The MUXEN
pin can be driven high to place the device in multiplexed operation or driven low to select non-multiplexed
operation. The MOTEN pin can be driven high to place the device in Motorola bus format or driven low to place the
device in Intel bus format.
Notes:
1. The CP2201 (28-pin package) can only be used in multiplexed mode.
2. The PCB traces connecting RD, WR, CS, ALE, and all address and data lines should be matched such that the
propagation delay does not vary by more than 5ns between any two signals.
A parallel interface read or write operation typically requires 260 ns (non-multiplexed) or 300 ns (multiplexed) to
transfer one byte of data. If back-to-back operations are scheduled on a non-multiplexed bus, data rates up to
30 Mbps can be achieved. Tables 26 through 29 provide detailed information about bus timing in each mode.
16.1. Non-Multiplexed Intel Format
Figure 22. Nonmuxed Intel READ
Valid Address
T
VD2
T
HOLD
T
VD1
T
AS
A[7:0]
D[7:0]
RD
Valid Data
T
RD
T
AHR
Notes:
1. CS must be asserted with or before RD.
2. WR must remain de-asserted during a READ.
Valid Address
T
DH
T
HOLD
T
WR
T
AS
A[7:0]
D[7:0]
WR
Valid Data
T
AHW
T
DS
Notes:
1. CS must be asserted with or before WR.
2. RD must remain de-asserted during a WRITE.
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