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| 型號(hào)： | CR16HCS9VJE8Y |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 50/157頁 |
| 文件大小： | 1256K |
| 代理商： | CR16HCS9VJE8Y |
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External Event Clock
The TnB I/O pin can be configured to operate as an external
event input clock for either of the two 16-bit counters. This in-
put can be programmed to detect either rising or falling edg-
es. The minimum pulse width of the external signal is one
system clock cycle. This means that the maximum frequency
at which the counter can run in this mode is one-half of the
system clock frequency. This clock source is not available in
the capture modes (modes 2 and 4) because the TnB pin is
used as one of the two capture inputs.
Pulse Accumulate Mode
The counter can also be configured to count prescaler output
clock pulses when the TnB is high and not count when TnB
is low, as illustrated in Figure 13. The resulting count is an in-
dicator of the cumulative time that TnB is high. This is called
the “pulse accumulate” mode. In this mode, an AND gate
generates a clock signal for the counter whenever a prescal-
er clock pulse is generated and TnB input is high. (The polar-
ity of the TnB signal is programmable, so the counter can
count when TnB is low rather than high.) The pulse accumu-
late mode is not available in the capture modes (modes 2 and
4) because the TnB pin is used as one of the two capture in-
puts.
Slow Clock
The slow clock is generated by the Dual Clock and Reset
(CLK2RES) module. The clock source is either the divided
fast clock or the external 32.768 kHz clock crystal (if available
and selected). The slow clock can be used as the clock
source for the two 16-bit counters. Because the slow clock
can be asynchronous to the system clock, a circuit is provid-
ed to synchronize the clock signal to the high-frequency sys-
tem clock before it is used for clocking the counters. The
synchronization circuit requires that the slow clock operate at
no more than one-fourth the speed of the system clock.
Limitations in Low-Power Modes
The Power Save mode uses the low-frequency clock as the
system clock. In this mode, the slow clock cannot be used as
a clock source for the timers because both CLK and SLCLK
are driven then at the same frequency, and the 2:1 system-
clock to input clock ratio needed for the synchronization can-
not be maintained. However, the External Event Clock and
Pulse Accumulate Mode will still work, as long as the external
event pulses are at least the size of the whole slow-clock pe-
riod. Using the prescaled system clock will also work, but at
a much slower rate than the original system clock.
Some Power Save modes stops the system clock (the high-
frequency and/or low-frequency clock) completely. If the sys-
tem clock is stopped, the timer stops counting until the sys-
tem clock resumes operation.
I
n the Idle or Halt mode, the system clock stops completely,
which stops the operation of the timers. In that case, the tim-
ers stop counting until the system clock resumes operation.
Figure 12.
Clock Source Block Diagram
Prescaler Register
TnPRSC
Prescaler Counter
5-bit
System
Clock
Reset
TnB
Pulse
Accumulate
External
Event
No Clock
Prescaled
Clock
Counter I
Clock
Select
Counter II
Clock
Select
Counter I
Clock
Counter II
Clock
Synchr.
Figure 13.
Pulse Accumulate Mode Operation
TnB
Prescaler Output
Counter Clock
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相關(guān)代理商/技術(shù)參數(shù) |
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| CR16HCS9VJE9 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of 16-bit CAN-enabled CompactRISC Microcontrollers |
| CR16HCS9VJI0 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of 16-bit CAN-enabled CompactRISC Microcontrollers |
| CR16HCS9VJI1 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of 16-bit CAN-enabled CompactRISC Microcontrollers |
| CR16HCS9VJI2 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of 16-bit CAN-enabled CompactRISC Microcontrollers |
| CR16HCS9VJI3 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of 16-bit CAN-enabled CompactRISC Microcontrollers |
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