參數(shù)資料
型號： CR16HCS9VJE8Y
英文描述： Microcontroller
中文描述： 微控制器
文件頁數(shù)： 79/157頁
文件大?。?/td> 1256K
代理商： CR16HCS9VJE8Y
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Acknowledge Cycle
The Acknowledge Cycle consists of two signals: the ac-
knowledge clock pulse the master sends with each byte
transferred, and the acknowledge signal sent by the receiv-
ing device (Figure 41).
Figure 41.
ACCESS.bus Data Transaction
The master generates the acknowledge clock pulse on the
ninth clock pulse of the byte transfer. The transmitter releas-
es the SDA line (permits it to go high) to allow the receiver to
send the acknowledge signal. The receiver must pull down
the SDA line during the acknowledge clock pulse, thus sig-
nalling the correct reception of the last data byte, and its
readiness to receive the next byte. Figure 42 illustrates the
acknowledge cycle.
Figure 42.
ACCESS.bus Acknowledge Cycle
The master generates an acknowledge clock pulse after
each byte transfer. The receiver sends an acknowledge sig-
nal after every byte received.
There are two exceptions to the “acknowledge after every
byte” rule.
1. When the master is the receiver, it must indicate to the
transmitter an end of data by not-acknowledging (“neg-
ative acknowledge”) the last byte clocked out of the
slave. This “negative acknowledge” still includes the ac-
knowledge clock pulse (generated by the master), but
the SDA line is not pulled down.
2. When the receiver is full, otherwise occupied, or a prob-
lem has occurred, it sends a negative acknowledge to
indicate that it can not accept additional data bytes.
Addressing Transfer Formats
Each device on the bus has a unique address. Before any
data is transmitted, the master transmits the address of the
slave being addressed. The slave device should send an ac-
knowledge signal on the SDA line, once it recognizes its ad-
dress.
The address is the first seven bits after a Start Condition. The
direction of the data transfer (R/W) depends on the bit sent
after the address — the eighth bit. A low-to-high transition
during a SCL high period indicates the Stop Condition, and
ends the transaction (Figure 43).
Figure 43.
A Complete ACCESS.bus Data Transaction
When the address is sent, each device in the system com-
pares this address with its own. If there is a match, the device
considers itself addressed and sends an acknowledge sig-
nal. Depending upon the state of the R/W bit (1:read, 0:write),
the device acts as a transmitter or a receiver.
The I
2
C bus protocol allows sending a general call address
to all slaves connected to the bus. The first byte sent speci-
fies the general call address (00
16
) and the second byte
specifies the meaning of the general call (for example, “Write
slave address by software only”). Those slaves that require
the data acknowledge the call and become slave receivers;
the other slaves ignore the call.
Arbitration on the Bus
Multiple master devices on the bus, require arbitration be-
tween their conflicting bus-access demands. Control of the
bus is initially determined according to address bits and clock
cycle. If the masters are trying to address the same IC, data
comparisons determine the outcome of this arbitration. In
master mode, the device immediately aborts a transaction if
the value sampled on the SDA lines differs from the value
driven by the device. (Exceptions to this rule are SDA while
receiving data; in these cases the lines may be driven low by
the slave without causing an abort).
The SCL signal is monitored for clock synchronization pur-
pose and allow the slave to stall the bus. The actual clock pe-
riod will be the one set by the master with the longest clock
period or by the slave stall period. The clock high period is
determined by the master with the shortest clock high period.
When an abort occurs during the address transmission, the
master that identify the conflict, give-up the bus and should
switch to slave mode and continue to sample SDA to see if it
is being addressed by the winning master on the AC-
CESS.bus.
19.2
The ACB module provides the physical layer for an AC-
CESS.bus compliant serial interface. The module is config-
urable as either a master or slave device. As a slave device,
the ACB module may issue a request to become the bus
master.
ACB FUNCTIONAL DESCRIPTION
S
P
Start
Condition
Stop
Condition
SDA
SCL
MSB
ACK
ACK
1
2 3 - 6
7
8
9
1
2
3 - 8
9
Acknowledgment
Signal From Receiver
Byte Complete
I
nterrupt Within
Receiver
Clock Line Held
Low by Receiver
While Interrupt
is Serviced
S
Start
Condition
SCL
1
2 3 - 6
7
8
9
Transmitter Stays Off
the Bus During the
Acknowledgment Clock
Acknowledgment
Signal From Receiver
Data Output
by
Transmitter
Data Output
by
Receiver
S
P
Start
Condition
Stop
Condition
SDA
SCL
1 - 7
8
9
1 - 7
8
9
1 - 7
8
9
Address R/W ACK
Data
ACK
Data
ACK
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