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| 型號： | CR16HCS9VJE8Y |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 62/157頁 |
| 文件大?。?/td> | 1256K |
| 代理商： | CR16HCS9VJE8Y |
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62
16.2.1
The Mode Control (MODE) registries a word-wide read/write
register which controls the mode selection of all four timer
subsystems. The register is cleared (0000
16
) upon reset.
15 14
13
12
TMOD4
T8RUN
T7RUN
Mode Control Register (MODE)
TxRUN
Timer start/stop. If set (1), the associated
counter and clock prescaler is started depend-
ing on the mode of operation. Once set, the
clock to the clock prescaler and the counter are
enabled and the counter will increment each
time the clock prescaler counter value matches
the value defined in the associated clock pres-
caler field (CxPRSC).
Timer System Operating Mode. This 2-bit wide
field enables or disables the Timer Subsystem
and defines it’s operating mode.
00:
Low-Power-Mode enabled. All clocks to
the counter subsystem are stopped. The
counter is stopped regardless of the val-
ue of the TxRUN bits. Read operations
to the Timer Subsystem will return the
last value; the user shall not perform any
write operations to the Timer Subsystem
while it is disabled since those will be ig-
nored.
01:
Dual 8-bit PWM mode enabled. Each 8-
bit counter may individually be started or
stopped via its associated TxRUN bit.
The TIOx pins will function as PWM out-
puts.
10:
16-bit PWM mode enabled. The two 8-
bit counters are concatenated to form a
single 16-bit counter. The counter may
be started or stopped with the lower of
the two TxRUN bits, i.e. T1RUN,
T3RUN, T5RUN and T7RUN. The TIOx
pins will function as PWM outputs.
11:
Capture Mode enabled. Both 8-bit
counters are concatenated and operate
as a single 16-bit counter. The counter
may be started or stopped with the lower
of the two TxRUN bits, i.e., T1RUN,
T3RUN, T5RUN and T7RUN. The TIOx
pins will function as capture inputs.
TMODx
16.2.2
The I/O Control Register 1 (IO1CTL) is a word-wide read/
write register. The register controls the functionality of the
I/O pins TIO1 through TIO4 depending on the selected mode
of operation. The register is cleared (0000
16
) upon reset.
15
14 12
11
10 8
P4POL
C4EDG
P3POL
C3EDG
I/O Control Register 1 (IO1CTL)
CxEDG
Capture Edge Control. Defines the polarity of a
capture event and the reset of the counter. The
value of this three bit field has no effect while
operating in PWM mode.
PxPOL
PWM Polarity. While operating in PWM mode
the bit defines the output polarity of the corre-
sponding PWM output (TIOx).
0 =
The PWM output is set (1) upon the 00
16
to 01
16
transition of the counter and will
be reset (0) once the counter value
matches the duty cycle value.
1 =
The PWM output is reset (0) upon the
00
16
to 01
16
transition of the counter and
will be set (1) once the counter value
matches the duty cycle value.
Once a counter is stopped, the output will assume the value
of PxPOL, i.e., its initial value. The PxPOL bit has no effect
while operating in capture mode.
16.2.3
The I/O Control Register 2 (IO2CTL) is a word-wide read/
write register. The register controls the functionality of the
I/O pins TIO5 through TIO8 depending on the selected mode
of operation. The register is cleared (0000) upon reset.
I/O Control Register 2 (IO2CTL)
The functionality of the bit fields of the IO2CTL register is
identical to the ones described in the IO1CTL register sec-
tion.
16.2.4
The Interrupt Control (INTCTL) register is a word-wide read/
write register. It contains the interrupt enable bits for all 16 in-
terrupt sources of the Versatile-Timer-Unit. Each interrupt en-
able bit corresponds to an interrupt pending flag located in
the Interrupt Pending Register (INTPND). All INTCTL regis-
ter bits are solely under software control. The register is
cleared (0000
16
) upon reset..
15
14
13
12
I4DEN I4CEN I4BEN I4AEN I3DEN I3CEN I3BEN I3AEN
Interrupt Control Register (INTCTL)
IxAEN
Timer x interrupt A enable. Enable/Disable an
interrupt request based on the corresponding
IxAPD flag being set. The associated IxAPD
11 10
TMOD3
9
8
T6RUN
T5RUN
7 6
TMOD2
5
4
3 2
TMOD1
1
0
T4RUN
T3RUN
T2RUN
T1RUN
7
6 4
C2EDG
3
2 0
C1EDG
P2POL
P1POL
CxEDG
Capture
Counter Reset
000
rising edge
No
001
falling edge
No
010
rising edge
Yes
011
falling edge
Yes
100
both edges
No
101
both edges
rising edge
110
both edges
falling edge
111
both edges
both edges
15
14 12
11
10 8
C7EDG
7
6 4
C6EDG P5POL
3
2 0
C5EDG
P8POL C8EDG
P7POL
P6POL
11
10
9
8
7
6
5
4
3
2
1
0
I2DEN I2CEN I2BEN I2AEN I1DEN I1CEN I1BEN I1AEN
相關(guān)PDF資料 |
PDF描述 |
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| CR16HCT5 | |
| CR16HCT5VJE7Y | Microcontroller |
| CR16HCT5VJE8Y | Microcontroller |
| CR16HCT5VJE9Y | Microcontroller |
| CR16HCT9 | |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| CR16HCS9VJE9 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of 16-bit CAN-enabled CompactRISC Microcontrollers |
| CR16HCS9VJI0 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of 16-bit CAN-enabled CompactRISC Microcontrollers |
| CR16HCS9VJI1 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of 16-bit CAN-enabled CompactRISC Microcontrollers |
| CR16HCS9VJI2 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of 16-bit CAN-enabled CompactRISC Microcontrollers |
| CR16HCS9VJI3 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of 16-bit CAN-enabled CompactRISC Microcontrollers |
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