參數(shù)資料
型號: CR16HCT9
文件頁數(shù): 1/157頁
文件大小: 1256K
代理商: CR16HCT9
2002 National Semiconductor Corporation
www.national.com
C
Interrupt
Control
February 2002
CR16MCS9/CR16MCS5/CR16HCS9/CR16HCS5
CompactRISC 16-Bit Reprogrammable/ROM
Microcontroller
1.0
General Description
The
CR16HCS5 CompactRISC microcontroller is based on a
Reduced Instruction Set Computer (RISC) architecture.
The device operates as a complete microcomputer with all
system timing, interrupt logic, flash program memory or
ROM memory, RAM, EEPROM data memory, and I/O ports
included on-chip. It is ideally suited to a wide range of em-
bedded controller applications because of its high perfor-
mance, on-chip integrated features and low power
consumption resulting in decreased system cost.
CR16MCS9/CR16MCS5
and
CR16HCS9/
The
CR16HCS5 offer the high performance of a RISC architec-
ture while retaining the advantages of a traditional Com-
plex Instruction Set Computer (CISC): compact code, on-
chip memory and I/O, and reduced cost. The CPU uses a
three-stage instruction pipeline that allows execution of up
to one instruction per clock cycle, or up to 24 million in-
structions per second (MIPS) at a clock rate of 24 MHz.
The
CR16MCS9/CR16MCS5
CR16HCS5 contain a FullCAN class, CAN serial interface
for low/high speed applications with 15 orthogonal mes-
sage buffers, each supporting standard as well as extend-
ed message identifiers.
CR16MCS9/CR16MCS5
and
CR16HCS9/
and
CR16HCS9/
TRI-STATE is a registered trademark of National Semiconductor Corporation.
64k-Byte
Flash
Program
Memory
CR16CAN
FullCAN 2.0B
Core Bus
Peripheral Bus
Clock Generator
Power-on-Reset
Slow Clk*
Processing
Unit
I/O
μ
Wire/SPI
12-ch
8-bit A/D
Fast Clk
3k-Byte
RAM
Peripheral
Bus
Controller
Bus
Interface
Unit
2176-Byte
EEPROM
Data
Memory
MIWU
2 Analog
Comparators
Timing
Watchdog
and
Power
Manage-
ment
2x
MFT
2x
USART
CR16B
RISC Core
ACCESS
bus
4x
VTU
Memory
1.5k-Byte
ISP
Please note that not all family members contain same peripheral modules and features.
Block Diagram
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