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| 型號(hào)： | CR16HCT5 |
| 文件頁(yè)數(shù)： | 113/157頁(yè) |
| 文件大?。?/td> | 1256K |
| 代理商： | CR16HCT5 |
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20.9.13 CAN Interrupt Pending Register (CIPND)
The CIPND register indicates any CAN Receive/Transmit In-
terrupt Requests caused by the message buffers 0..14 and
CAN error occurrences.
15
14
EIPND
IPND[14:0]
0
r
EIPND
Error Interrupt Pending — EIPND indicates the
status change of TEC/REC and will execute an
error interrupt if EIEN is set. The user has the
responsibility to reset EIPND by means of the
CICLR register.
“0”
CAN status is not changed
“1”
CAN status is changed
Buffer Interrupt Pending — IPND[14:0] bits are
set by CR16CAN following a successful trans-
mission or reception of a message to or from
message buffer 0...14, IPND14 for buffer 14
and IPND0 for buffer 0.
“0”
no interrupt pending for this message buff-
er
“1”
message buffer has generated an inter-
rupt
IPND[14:0]
20.9.14 CAN Interrupt Clear Register (CICLR)
The bits in the CICLR register separately clear all CAN inter-
rupt pending flags caused by the message buffers 0...14 and
from the Error Management Logic.
15
14
EICLR
ICLR[14:0]
0
w
EICLR
Error Interrupt Clear. The EICLR bit can clear
the EIPND bit:
“0” the contents of the EIPND bit is un-
changed
“1” the contents of the EIPND bit is reset
Buffer Interrupt Clear. The user is able to clear
the buffer interrupt pending bits by ICLR[14:0]:
“0” the contents of the respective IPND bit is
unchanged
“1” the contents of the respective IPND bit is
reset
ICLR[14:0]
20.9.15 CAN Interrupt Code Enable Register (CICEN)
The CAN Interrupt Code Enable Register (CICEN) deter-
mines whether the interrupt pending flag in IPND should be
translated into the Interrupt Code field of the CSTPND regis-
ter. All interrupt requests, CAN error and buffer 0...14 inter-
rupts can be enabled/disabled separately for the interrupt
code indication field.
15
14
EICEN
0
r/w
EICEN
Error Interrupt Code Enable:
“0”
error interrupt pending is not indicated in
the interrupt code
“1”
error interrupt pending is indicated in the
interrupt code
Buffer Interrupt Code Enable:
“0”
buffer interrupt pending is not indicated in
the interrupt code
“1”
buffer interrupt pending is indicated in the
interrupt code
ICEN[14:0]
20.9.16 CAN Status Pending Register (CSTPND)
The CAN Status Pending Register (CSTPND) contains the
status of the CAN Node and the Interrupt Code.
15
8
7
Reserved
NS[2:0]
0
r
NS[2:0]
CAN Node Status. This bits indicate the status
of the CAN node as it is described in Table 35.
IRQ,IST[3:0] Interrupt Code. This section of the Status
Pending Register represents the interrupt
source of the highest priority interrupt currently
pending and enabled in the CICEN register.
Table 36 shows the several interrupt codes for
CICEN=FFFF.
0
0
0
ICEN[14:0]
5
4
3
0
IRQ
IST[3:0]
Table 35
CAN Node Status
NS2
NS1
NS0
Node Status
0
0
0
1
1
0
1
1
0
1
0
0
1
X
X
Not Active
Error active
Error Warning Level
Error passive
Bus off
Table 36
Highest Priority Interrupt Code
(CICEN = FFFF)
CAN interrupt
request
IRQ
IST3
IST2
IST1
IST0
no request
Error interrupt
Buffer 0
Buffer 1
Buffer 2
Buffer 3
Buffer 4
Buffer 5
Buffer 6
Buffer 7
Buffer 8
Buffer 9
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
1
0
1
0
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