- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366891 > CR16HCT5 PDF資料下載
參數(shù)資料
| 型號： | CR16HCT5 |
| 文件頁數(shù)： | 38/157頁 |
| 文件大?。?/td> | 1256K |
| 代理商： | CR16HCT5 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁當前第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁
www.national.com
38
11.6.2
A transition from the Active mode to the Power Save mode is
accomplished by writing a 1 to the PMCSR.PSM bit. The
transition to Power Save mode is either initiated immediately
or upon execution of the next WAIT instruction, depending on
the PMCSR.WBPSM bit.
For an immediate transition to Power Save mode (PMC-
SR.WBPSM=0), the CPU continues to operate using the low-
frequency clock. The PMCSR.PSM bit is set to 1 when the
transition to the Power Save mode is completed.
For a transition upon the next WAIT instruction (PMC-
SR.WBPSM=1), the CPU continues to operate in the Active
mode until it executes a WAIT instruction. Upon execution of
the WAIT instruction, the device enters the Power Save
mode and the CPU waits for the next interrupt event. In this
case, the PMCSR.PSM bit is set to 1 when it is written, even
before the WAIT instruction is executed.
Active to Power Save Mode
11.6.3
Entry into the Idle mode is accomplished by writing a 1 to the
PMCSR.IDLE bit and then executing a WAIT instruction.
The Idle mode can be entered only from the Active or Power
Save mode. For entry from the Active mode, the PMC-
SR.WBPSM bit must be set before the WAIT instruction is ex-
ecuted.
Entering the Idle Mode
11.6.4
In systems where the low-frequency crystal is available and
is used to generate the Slow Clock (SLCLK), power con-
sumption can be reduced further in the Power Save or Idle
mode by disabling the high-frequency clock. This is accom-
plished by writing a 1 to the PMCSR.DHF bit before execut-
ing the WAIT instruction that puts the device in the Power
Save or Idle mode. The high-frequency clock is turned off
only after the device enters the Power Save or Idle mode.
The CPU operates on the low-frequency clock in Power Save
mode. It can turn off the high-frequency clock at any time by
writing a 1 to the PMCSR.DHF bit.
The high-frequency oscillator is always enabled in Active
mode and always disabled in Halt mode, regardless of the
PMCSR.DHF bit setting.
Immediately following power-up and entry into the Active
mode, the software must wait for the low-frequency clock to
become stable before it can put the device in the Power Save
mode. It should monitor the PMCSR.OLFC bit for this pur-
pose. Once this bit is set to 1, the slow clock is stable and the
Power Save mode can be entered.
Disabling the High-Frequency Clock
11.6.5
Entry into the Halt mode is accomplished by writing a 1 to the
PMCSR.HALT bit and then executing a WAIT instruction.
The Halt mode can be entered only from the Active or Power
Save mode. For entry from the Active mode, the PMC-
SR.WBPSM bit must be set before the WAIT instruction is ex-
ecuted.
Entering the Halt Mode
11.6.6
A transition from the Power Save mode to the Active mode
can be accomplished by either a software command or a
hardware wake-up event. The software method is to write a
0 to the PMCSR.PSM bit. The value of the register bit chang-
es only after the transition to the Active mode is completed.
If the high-frequency oscillator is disabled for Power Save op-
eration, the oscillator must be enabled and allowed to stabi-
lize before the transition to Active mode. To enable the high-
frequency oscillator, the software writes a 0 to the PMC-
SR.DHF bit. Before writing a 0 to the PMCSR.PSM bit, the
software should first monitor the PMCSR.OHFC bit to deter-
mine whether the oscillator has stabilized.
Software-Controlled Transition to Active Mode
11.6.7
A hardware wake-up event switches the device directly from
Power Save, Idle, or Halt mode to the Active mode.
Hardware wake-up events are:
a Non-Maskable Interrupt (NMI)
a valid wake-up event on a Multi-Input Wake-Up channel
When a wake-up event occurs, the on-chip hardware per-
forms the following steps:
1. Clears the PMCSR.DHF bit, thus enabling the high-fre-
quency clock (if it was disabled).
2. Waits for the PMCSR.OHFC bit to be set, which indi-
cates that the high-frequency clock is operating and is
stable.
3. Switches the device into the Active mode.
Wake-Up Transition to Active Mode
11.6.8
The Power Management Module has several mechanisms to
protect the device from malfunctions caused by missing or
unstable clock signals.
The PMCSR.OHFC and PMCSR.OLFC bits indicate the cur-
rent status of the high-frequency and low-frequency clock os-
cillators, respectively. The software can check the
appropriate bit before it changes to an operating mode that
requires the clock. A status bit set to 1 indicates an operating,
stable clock. A status bit cleared to 0 indicates a clock that is
disabled, not available, or not yet stable.
During a power mode transition, if there is a request to switch
to a mode that uses clock with its status bit cleared to 0, the
switch is delayed until that bit is set to 1 by the hardware.
When the system is built without an external crystal network
for the low-frequency clock, the high-frequency clock is divid-
ed by a prescaler factor to produce the low-frequency clock.
In this situation, the high-frequency clock is disabled only in
the Halt mode, and cannot be disabled for the Power Save or
Idle mode, regardless of the software command issued
.
Without an external crystal network for the low-frequency
clock, the device comes out of the Halt or Idle mode and en-
ters the Active mode with the high-speed oscillator used as
the clock. The device can still enter the Power Save from the
Active mode by using the high-frequency-clock divider to
generate the slow clock (PMCSR.DHF=0).
Note:
For correct operation in the absence of a low-frequen-
cy crystal, the X2CKI pin must be tied low (not left floating) so
that the hardware can detect the absence of the crystal.
Power Mode Switching Protection
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CR16HCT5VJE7Y | Microcontroller |
| CR16HCT5VJE8Y | Microcontroller |
| CR16HCT5VJE9Y | Microcontroller |
| CR16HCT9 | |
| CR16HCT9VJE7 | Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CR16HCT5VJE7Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT5VJE8Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT5VJE9Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT5VJEXY | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller |
| CR16HCT9 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。