參數(shù)資料
型號： CR16HCT5
文件頁數(shù)： 139/157頁
文件大小： 1256K
代理商： CR16HCT5
139
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Flash EEPROM Data Programming
Flash EEPROM ISP-Memory Programming
Symbol
Parameter
Conditions
Min
Max
Units
re-programming time
a
Programming pulse width
b
Erase pulse width
c
Charge pump power-up time
d
Program/erase transition time
e
Charge pump enable hold time
a. One re-programming cycle involves one erase pulse followed by programming of four bytes.
1.32
30
4
10
5
1
-
ms
μ
s
ms
μ
s
μ
s
clock
cycles
μ
s
cycles
cycles
years
t
PWD
t
EWD
t
SDD
t
TTD
t
PED
b. The programming pulse width is determined by the following equation:
t
PWD
= T
clk
x (FTDIV+1) x (FTPROG+1), where T
clk
is the system clock period, FTDIV is the contents of the DMPSLR register
and FTPROG is the contents of the DMPROG register.
40
-
-
-
-
c. The erase pulse width is determined by the following equation:
t
EWD
= T
clk
x (FTDIV+1) x 4 x (FTER+1), where T
clk
is the system clock period, FTDIV is the contents of the DMPSLR register
and FTER is the contents of the DMERASE register.
d. The program/erase start delay time is determined by the following equation:
t
SDD
= T
clk
x (FTDIV+1) x (FTSTART+1), where T
clk
is the system clock period, FTDIV is the contents of the DMPSLR register
and FTSTART is the contents of the DMSTART register.
e. The program/erase transition time is determined by the following equation:
t
TTD
= T
clk
x (FTDIV+1) x (FTTRAN+1), where T
clk
is the system clock period, FTDIV is the contents of the DMPSLR register
and FTTRAN is the contents of the DMTRAN register.
t
EDD
Charge pump power hold time
f
Write/erase endurance (high endurance)
Write/erase endurance (low endurance)
Data retention
f. The program/erase end delay time is determined by the following equation:
t
EDD
= T
clk
x (FTDIV+1) x (FTEND+1), where T
clk
is the system clock period, FTDIV is the contents of the DMPSLR register and
FTEND is the contents of the DMEND register.
5
-
-
-
-
100,000
25,000
100
Symbol
Parameter
Conditions
Min
Max
Units
t
PWI
t
EWI
Programming pulse with
a
Erase pulse width
b
Data retention
a. Programming timing is controlled by the flash EEPROM data memory interface
b. Erase timing is controlled by the flash EEPROM data memory interface
30
1
100
-
40
-
-
μ
s
ms
years
cycles
100K
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