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| 型號(hào)： | CR16HCT5 |
| 文件頁(yè)數(shù)： | 47/157頁(yè) |
| 文件大小： | 1256K |
| 代理商： | CR16HCT5 |
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LTWCP
Lock TWCP Register. When cleared to 0, ac-
cess to the TWCP register is allowed. When
set to 1, the TWCP register is locked.
Lock TWMT0 Register. When cleared to 0, ac-
cess to the TWMT0 and T0CSR registers are
allowed. When set to 1, the TWMT0 and
T0CSR registers are locked.
Lock LDWCNT Register. When cleared to 0,
access to the LDWCNT register is allowed.
When set to 1, the LDWCNT register is locked.
WATCHDOG Clock from T0IN. When cleared
to 0, the T0OUT signal (the output of Timer T0)
is used as the WATCHDOG clock. When set to
1, the T0IN signal (the prescaled slow clock) is
used as the WATCHDOG clock.
WATCHDOG Service Data Match Enable.
When cleared to 0, WATCHDOG servicing is
accomplished by writing a count value to the
WDCNT register; write operations to the
WATCHDOG Service Data Match (WDSDM)
register are ignored. When set to 1, WATCH-
DOG servicing is accomplished by writing the
value 5C hex to the WDSDM register.
LTWMT0
LWDCNT
WDCT0I
WDSDME
14.4.2
Timer and WATCHDOG Clock Prescaler
Register (TWCP)
The TWCP register is a byte-wide, read/write register that
defines the prescaler value used for dividing the low frequen-
cy clock to generate the T0IN clock. Upon reset, the non-re-
served bits of the register are cleared to 0. The register
format is shown below.
7
6
5
4
Reserved
MDIV
Main Clock Divide. This 3-bit field defines the
prescaler factor used for dividing the low speed
device clock to create the T0IN clock. The al-
lowed 3-bit values and the corresponding clock
divisors and clock rates are listed below.
MDIV
Clock Divisor TOIN Frequency
(fSCLK=32.768 kHz)
000
1
001
2
010
4
011
8
100
16
101
32
other
Reserved
14.4.3
The TWMT0 register is a word-wide, read/write register that
defines the T0OUT interrupt rate. Upon reset, TWMT0 regis-
ter is initialized to FFFF hex. The register format is shown be-
low.
15 14 13 12 11 10 9
8
PRESET
TWM Timer 0 Register (TWMT0)
PRESET
Timer T0 Preset. Timer T0 is reloaded with this
value on each underflow. Thus, the frequency
of the Timer T0 interrupt is the frequency of
T0IN divided by (PRESET+1). The allowed val-
ues of PRESET are 0001 hex through FFFF
hex.
14.4.4
The T0CSR register is a byte-wide, read/write register that
controls Timer T0 and shows its current status. Upon reset,
the non-reserved bits of the register are cleared to 0. The
register format is shown below.
7
6
5
4
Reserved
TWMT0 Control and Status Register (T0CSR)
RST
Restart. When this bit is set to 1, it forces the
timer to reload the value in the TWMT0 register
on the next rising edge of the selected input
clock. The RST bit is reset automatically by the
hardware on the same rising edge of the se-
lected input clock. Writing a 0 to this bit position
has no effect. Upon reset, the non-reserved
bits of the register are cleared to 0.
Terminal Count. This bit is set to 1 by the hard-
ware when the Timer T0 count reaches zero
and is cleared to 0 when the software reads the
T0CSR register. It is a read-only bit. Any data
written to this bit position is ignored.
Timer T0 Interrupt Enable. When this bit is set
to 1, it enables an interrupt to the CPU each
time the Timer T0 count reaches zero. When
this bit is cleared to 0, Timer T0 interrupts are
disabled.
TC
T0INTE
14.4.5
The WDCNT register is a byte-wide, write-only register that
holds the value that is loaded into the WATCHDOG counter
each time the WATCHDOG is serviced. The WATCHDOG is
started by the first write to this register. Each successive write
to this register restarts the WATCHDOG count with the writ-
ten value. Upon reset, this register is initialized to 0F hex.
WATCHDOG Count Register (WDCNT)
14.4.6
WATCHDOG Service Data Match Register
(WDSDM)
The WSDSM register is a byte-wide, write-only register used
for servicing the WATCHDOG. When this type of servicing is
enabled (TWCFG.WDSDME=1), the WATCHDOG is ser-
viced by writing the value 5C hex to the WSDSM register.
Each such servicing reloads the WATCHDOG counter with
the value previously written to the WDCNT register. Writing
any data other than 5C hex triggers a WATCHDOG error.
Writing to the register more than once in one WATCHDOG
clock cycle also triggers a WATCHDOG error signal. If this
type of servicing is disabled (TWCFG.WDSDME=0), any
write to the WSDSM register is ignored.
14.5
WATCHDOG PROGRAMMING
PROCEDURE
The highest level of protection against software errors is
achieved by programming and then locking the WATCHDOG
registers and using the WDSDM register for servicing. This is
the procedure:
3
2
1
0
MDIV
32.768 kHz
16.384 kHz
8.192 kHz
4.096 kHz
2.056 kHz
1.024 kHz
N/A
7
6
5
4
3
2
1
0
3
2
1
0
T0INTE
TC
RST
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