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| 型號(hào)： | CR16HCT5 |
| 文件頁(yè)數(shù)： | 52/157頁(yè) |
| 文件大小： | 1256K |
| 代理商： | CR16HCT5 |
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The TnA and TnB pins function as capture inputs. A transition
received on the TnA pin transfers the timer contents to the
TnCRA register. Similarly, a transition received on the TnB
pin transfers the timer contents to the TnCRB register. Each
input pin can be configured to sense either rising or falling
edges.
The TnA and TnB inputs can be configured to preset the
counter to FFFF hex upon reception of a valid capture event.
In this case, the current value of the counter is transferred to
the corresponding capture register and then the counter is
preset to FFFF hex. Using this approach allows the software
to determine the on-time and off-time and period of an exter-
nal signal with a minimum of CPU overhead.
The values captured in the TnCRA register at different times
reflect the elapsed time between transitions on the TnA pin.
The same is true for the TnCRB register and the TnB pin. The
input signal on TnA or TnB must have a pulse width equal to
or greater than one system clock cycle.
There are three separate interrupts associated with the cap-
ture timer, each with its own enable bit and pending flag. The
three interrupt events are reception of a transition on TnA, re-
ception of a transition on TnB, and underflow of the TnCNT1
counter. The enable bits for these events are TnAIEN, TnBI-
EN, and TnCIEN, respectively.
In Mode 2, Timer/Counter II (TnCNT2) can be used as a sim-
ple system timer. The clock counts down using the clock se-
lected with the Timer/Counter II clock selector. It generates
an interrupt upon each underflow if the interrupt is enabled
with the TnDIEN bit.
Neither Timer/Counter I (TnCNT1) nor Timer/Counter II
(TnCNT2) can be configured to operate as an external event
counter or to operate in the pulse accumulate mode because
the TnB input is used as a capture input. Attempting to select
one of these configurations will cause one or both counters
to stop.
15.2.3
Mode 3 is the Dual Independent Timer mode, which gener-
ates system timing signals or counts occurrences of external
events.
Figure 16 is a block diagram of the Multi-Function Timer con-
figured to operate in Mode 3. The timer is configured to oper-
ate as a dual independent system timer or dual external
event counter. In addition, Timer/Counter I can generate a
50% duty cycle PWM signal on the TnA pin. The TnB pin can
be used as an external event input or pulse accumulate input
and can be used as the clock source for either Timer/Counter
I or Timer/Counter II. Both counters can also be clocked by
the prescaled system clock.
Mode 3: Dual Independent Timer/Counter
Figure 15.
Mode 2: Dual Input Capture Block Diagram
Capture A
TnCRA
Timer/Counter I
TnCNT1
Capture B
TnCRB
Timer/Counter II
TnCNT2
Timer I
Clock
Timer II
Clock
TnB
TnA
TnAIEN
TnAPND
Timer
Interrupt I
TnBIEN
TnBPND
Timer
Interrupt I
TnCIEN
TnCPND
Timer
Interrupt I
Underflow
TnDIEN
TnDPND
Timer
Interrupt II
Underflow
TnAEN
Preset
Preset
TnBEN
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