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| 型號(hào)： | CR16HCT9 |
| 文件頁(yè)數(shù)： | 15/157頁(yè) |
| 文件大小： | 1256K |
| 代理商： | CR16HCT9 |
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7.0
CPU and Core Registers
The device uses the same CR16B CPU core as other Com-
pactRISC family members. The core's Reduced Instruction
Set Computer (RISC) architecture allows a processing rate
of up to one instruction per clock cycle.
The CPU core uses a set of internal registers:
— General-purpose registers (R0-R13, RA, and SP)
— Dedicated address registers (PC, ISP, and INTBASE)
— Processor Status Register (PSR)
— Configuration Register (CFG)
All of these registers are 16 bits wide except for the three ad-
dress registers, which are 21 bits wide.
Some register bits are designated as “reserved.” The CPU
must write a zero to each of these bit locations when it writes
to the register. Read operations from reserved bit locations
return undefined values.
7.1
There are 16 general-purpose registers, designated R0
through R13, RA, and SP. Registers R0 through R13 can be
used for any purpose such as holding variables, addresses,
or index values. The RA register is usually used to store the
return address upon entry into a subroutine. The SP register
is usually used as the pointer to the program run-time stack.
If a general-purpose register is used for a byte-wide opera-
tion, only the low-order byte is referenced or modified. The
high-order byte is not used or affected by a byte-wide opera-
tion.
GENERAL-PURPOSE REGISTERS
7.2
There are three dedicated address registers: the Program
Counter (PC), the Interrupt Stack Pointer (ISP), and the Inter-
rupt Base Register (INTBASE). Each of these registers is 21
bits wide.
DEDICATED ADDRESS REGISTERS
7.2.1
The PC register contains the address of the least significant
word currently being fetched. It is automatically incremented
or changed by the appropriate amount each time an instruc-
tion is executed.
The least significant bit of the PC is always zero, thus instruc-
tions must always be aligned to an even address in the range
of 0000 to 1FFFE hex.
Upon reset, the PC register is initialized to zero and program
execution starts at that address (if in IRE-Mode). When a re-
set signal is received, bits 1 through 16 of the PC register
(prior to initialization) are stored in register R0. This allows
the software to determine the point in the program at which
the reset occurred.
Program Counter
7.2.2
The ISP register points to the lowest address of the last item
stored on the interrupt stack. This stack is used by the hard-
ware when an interrupt or trap service procedure is invoked.
Interrupt Stack Pointer
7.2.3
The INTBASE register holds the address of the Dispatch Ta-
ble for interrupts and traps. The least significant bit of the reg-
ister is always zero. Thus, the Dispatch Table starts at an
even address in the range of 0000 to FFFE.
Interrupt Base Register
7.3
The Processor Status Register (PSR) holds status informa-
tion and selects the operating modes for the CPU core. The
format of the register is shown below.
15 14 13 12 11 10 9
8
Reserved
I
P
E
0
PROCESSOR STATUS REGISTER
C bit
The Carry (C) bit indicates whether a carry or
borrow occurred after addition or subtraction. It
is set to 1 if a carry or borrow occurred, or
cleared to 0 otherwise.
The Trace (T) bit, when set, causes a Trace
(TRC) trap to be executed after every instruc-
tion. This bit is automatically cleared to 0 when
a trap or interrupt occurs.
The Low (L) bit is set by comparison opera-
tions. In a comparison of unsigned integers, the
bit is set to 1 if the second operand (Rdest) is
less than the first operand (Rsrc). Otherwise, it
is cleared to 0.
The Flag (F) bit is a general condition flag that
is set by various instructions. It may be used to
signal exception conditions or to distinguish the
results of an instruction. For example, integer
arithmetic instructions use this bit to indicate an
overflow condition after an addition or subtrac-
tion operation.
The Zero (Z) bit is set by comparison opera-
tions. In a comparison of integers, the bit is set
to 1 if the two operands are equal. Otherwise,
it is cleared to 0.
The Negative (N) bit is set by comparison oper-
ations. In a comparison of signed integers, the
bit is set to 1 if the second operand (Rdest) is
less than the first operand (Rsrc). Otherwise, it
is cleared to 0.
The Local Maskable Interrupt Enable (E) bit is
used to enable or disable maskable interrupts.
If this bit and the Global Maskable Interrupt En-
able (I) bit are both set to 1, all maskable inter-
rupts are accepted. Otherwise, only the non-
maskable interrupt is accepted. The E bit is set
to 1 by the Enable Interrupts (EI) instruction
and cleared to 0 by the Disable Interrupts (DI)
instruction.
The Trace Trap Pending (P) bit is used togeth-
er with the Trace (T) bit to prevent a Trace
(TRC) trap from occurring more than once for
any instruction. The P bit may be cleared to 0
(no TRC trap pending) or set to 1 (TRC trap
pending).
T bit
L bit
F bit
Z bit
N bit
E bit
P bit
7
N
6
Z
5
F
4
0
3
0
2
L
1
T
0
C
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