參數(shù)資料
型號： CR16HCT9
文件頁數(shù)： 33/157頁
文件大?。?/td> 1256K
代理商： CR16HCT9
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Both the E bit and I bit can be controlled with the Load Pro-
cessor Register (LPR) instruction. In addition, the E bit is
easily changed by executing the Enable Interrupts (EI) or
Disable Interrupts (DI) instruction. Using the EI and DI in-
structions avoids the possibility of an interrupt occurring with-
in a read-modify-write operation on the PSR register.
10.4
The Interrupt Control Unit uses the following interrupt control
and status registers:
— Non-Maskable Interrupt Status Register (NMISTAT)
— Non-Maskable Interrupt Status Monitor Reg. (NMIMN-
TR)
— External NMI Control/Status Register (EXNMI)
— Interrupt Enable and Mask Register 0 (IENAM0)
— Interrupt Enable and Mask Register 1 (IENAM1)
— Interrupt Vector Register (IVCT)
INTERRUPT REGISTERS
Figure 5.
INTBASE
~
~
~
~
Non-maskable Interrupt
Reserved
Supervisor Call Trap
Divide By Zero Trap
Flag Trap
Breakpoint Trap
Trace Trap
Undefined Instruction Trap
Maskable Interrupts
NMI
Reserved
Reserved
SVC
DVZ
FLG
BPT
TRC
UND
Reserved
Reserved
ISE
INTn
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 to 127
In-System Emulator Interrupt
31
0
Reserved
Reserved
DBG
Debug Trap
Table 11
Maskable Interrupt Priority List
Interrupt Request
Source
IRQ31
IRQ30
IRQ29
IRQ28
IRQ27
IRQ26
IRQ25
IRQ24
IRQ23
IRQ22-IRQ19
IRQ18
IRQ17
IRQ16
IRQ15
IRQ14
IRQ13
IRQ12
IRQ11
IRQ10
IRQ9
RTI (Timer 0), highest priority
T1A (Timer 1 input A)
T1B (Timer 1 input B)
T2A (Timer 2 input A)
T2B (Timer 2 input B)
VTUA (VTU Interrupt Request 1)
VTUB (VTU Interrupt Request 2)
VTUC (VTU Interrupt Request 3)
VTUD (VTU Interrupt Request 4)
Reserved
CAN
Reserved
USART1 Rx
USART2 Rx
ACCESS.bus
MICROWIRE/SPI Rx/Tx
Reserved
USART1 Tx
USART2 Tx
MIWU16 Interrupt 0
IRQ8
IRQ7
IRQ6
IRQ5
IRQ4-IRQ2
IRQ1
IRQ0
MIWU16 Interrupt 1
MIWU16 Interrupt 2
MIWU16 Interrupt 3
ADC
Reserved
Flash Program Memory
Reserved, lowest priority
Table 11
Maskable Interrupt Priority List
Interrupt Request
Source
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