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| 型號(hào)： | CR16HCT9 |
| 文件頁(yè)數(shù)： | 42/157頁(yè) |
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13.0
Multi-Input Wake-Up
The Multi-Input Wake-Up (MIWU16) module monitors its 16
input channels for a software-selectable trigger condition.
Upon detection of a trigger condition, the module generates
an interrupt request and if enabled, a wake-up request. A
wake-up request can be used by the power management unit
to exit the Halt, Idle, or Power Save mode and return to the
active mode. An interrupt request generates an interrupt to
the CPU (interrupt IRQ2), allowing interrupt processing in re-
sponse to external events.
The wake-up event only activates the clocks and CPU, but
does not by itself initiate execution of any code. It is the inter-
rupt request associated with the MIWU16 that gets the CPU
to start executing code, by jumping to the proper interrupt
routine. Therefore, setting up the MIWU16 interrupt handler
is essential for any wake-up operation.
There are four interrupt requests that can be routed to the
ICU as shown in Figure 9. Each of the 16 MIWU channels
can be programmed to activate one of these four interrupt re-
quests.
The input pins for the Multi-Input Wake-Up channels are
named WUI0 through WUI15.
WUI0
WUI1
WUI2
WUI3
WUI4
WUI5
WUI6
WUI7
WUI8
WUI9
WUI10
WUI11
WUI12
WUI13
WUI14
WUI15
Each input can be configured to trigger on rising or falling
edges, as determined by the setting in the WKEDG register.
Each trigger event is latched into the WKPND register. If a
trigger event is enabled by its respective bit in the WKENA
register, an active wake-up/interrupt signal is generated. The
software can determine which channel has generated the ac-
tive signal by reading the WKPND register.
The Multi-Input Wake-Up module is active at all times, includ-
ing the Halt mode. All device clocks are stopped in this mode.
Therefore, detecting an external trigger condition and the
subsequent setting of the pending flag are not synchronous
to the system clock.
13.1
WAKE-UP EDGE DETECTION REGISTER
(WKEDG)
The Wake-Up Edge Detection (WKEDG) register is a word-
wide read/write register that controls the edge sensitivity of
the Multi-Input Wake-Up pins. Register bits 0 through 15 con-
trol input pins WUI0 through WUI15, respectively. A bit
cleared to 0 configures the corresponding input to trigger on
a rising edge (a low-to-high transition). A bit set to 1 config-
ures the corresponding input to trigger on a falling edge (a
high-to-low transition).
This register is cleared upon reset, which configures all 16 in-
puts to be triggered on rising edges.
The register format is shown below.
15
WKED15-WKED0
13.2
The Wake-Up Enable (WKENA) register is a word-wide read/
write register that enables or disables each of the Multi-Input
Wake-Up channels. Register bits 0 through 15 control chan-
nels WUI0 through WUI15, respectively. A bit cleared to 0
disables the wake-up function and a bit set to 1 enables the
function.
This register is cleared upon reset, which disables all eight
wake-up/interrupt channels.
WAKE-UP ENABLE REGISTER (WKENA)
PL0
PL1
PL2
PL3
PH0
PH1
PH2
PH3
TWM-T0OUT
ACCESS.bus
Canards
MWCS
RDX1
RDX2
Comparator 1
Comparator 2
0
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