參數(shù)資料
型號： CR16HCT9
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代理商： CR16HCT9
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cleared (0), operation of the pin for the timer/
counter is disabled.
TnB Enable. When set (1), the TnB pin in en-
abled to operate in Mode 2 (Dual Input Cap-
ture) or Mode 4 (Single Input Capture and
Single Timer). A transition on the TnB pin pre-
sets the corresponding timer/counter to FFFF
hex (TnCNT1 in Mode 2 or TnCNT2 in Mode
4). When this bit is cleared (0), operation of the
pin for the timer/counter is disabled. This bit
setting has no effect in Mode 1 or Mode 3.
TnA Output Data. This is a status bit that indi-
cates the current state of the TnA pin when the
pin is used as a PWM output. When set (1), the
TnA pin is high; when cleared (0), the TnA pin
is low. The hardware sets and clears this bit,
but the software can also read or write this bit
at any time and thus control the state of the out-
put pin. In case of conflict, a software write has
precedence over a hardware update. This bit
setting has no effect when TnA is used as an
input.
TnBEN
TnAOUT
15.5.8
The Timer Interrupt Control (TnICTL) register is a byte-wide,
read/write register that contains the interrupt enable bits and
interrupt pending bits for the four timer interrupt sources,
designated A, B, C, and D. The condition that causes each
type of interrupt depends on the operating mode, as shown
in Table 15.
This register is cleared upon reset. The register format is
shown below.
Timer Interrupt Control Register (TnICTL)
TnAPND
Timer Interrupt Source A Pending. When this
bit is set (1), it indicates that timer interrupt con-
dition “A” has occurred. When this bit is cleared
(0), it indicates that the interrupt condition has
not occurred. For an explanation of interrupt
conditions A, B, C, and D, see Table 15
This bit can be set by the hardware or by the
software. To clear this bit, the software must
use the Timer Interrupt Clear Register (TnI-
CLR). Any attempt by the software to directly
write a 0 to this bit is ignored.
Timer Interrupt Source B Pending. See the de-
scription of TnAPND.
Timer Interrupt Source C Pending. See the de-
scription of TnAPND.
Timer Interrupt Source D Pending. See the de-
scription of TnAPND.
Timer Interrupt A Enable. When set (1), this bit
enables an interrupt on each occurrence of in-
terrupt condition “A.” When cleared (0), an oc-
currence of interrupt condition “A” does not
generate an interrupt to the CPU, but still sets
the associated pending flag (TnAPND). For an
explanation of interrupt conditions A, B, C, and
D, see Table 15.
Timer Interrupt B Enable. See the description
of TnAIEN.
TnBPND
TnCPND
TnDPND
TnAIEN
TnBIEN
TnCIEN
Timer Interrupt C Enable. See the description
of TnAIEN.
Timer Interrupt D Enable. See the description
of TnAIEN.
TnDIEN
15.5.9
The Timer Interrupt Clear (TnICLR) register is a byte-wide,
write-only register that allows the software to clear the TnAP-
ND, TnBPND, TnCPND, and TnDPND bits in the Timer Inter-
rupt Control (TnICTRL) register. The register format is shown
below.
7 6 5 4
3
2
Reserved
TnDCLR
TnCCLR
Timer Interrupt Clear Register (TnICLR)
TnACLR
Timer Pending A Clear. When written with a 1,
the Timer Interrupt Source A Pending bit
(TnAPND) is cleared in the Timer Interrupt
Control register (TnICTL). Writing a 0 to the
TnACLR bit has no effect.
Timer Pending B Clear. See the description of
TnACLR.
Timer Pending C Clear. See the description of
TnACLR.
Timer Pending D Clear. See the description of
TnACLR.
TnBCLR
TnCCLR
TnDCLR
7
6
5
4
3
2
1
0
TnDIEN
TnCIEN
TnBIEN
TnAIEN
TnDPND
TnCPND
TnBPND
TnAPND
1
0
TnBCLR
TnACLR
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