參數(shù)資料
型號(hào): CR16HCT9
文件頁(yè)數(shù): 109/157頁(yè)
文件大?。?/td> 1256K
代理商: CR16HCT9
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“0”
“1”
level of the CAN receive pin CANRX.
“0”
dominate state is “0”; recessive state is “1”
“1”
dominate state is “1”; recessive state is “0”
Buffer Lock. With this bit the user can configure
the buffer lock function. If this feature is en-
abled, a buffer will be locked upon a successful
frame reception. The buffer will be unlocked
again by writing RX_READY in the buffer sta-
tus register, i.e., after reading data.
“0”
lock function is disabled for all buffers
“1”
lock function is enabled for all buffers
Time Sync Enable. The Time Sync bit enables
or disables the time stamp synchronization
function of the CR16CAN.
“0”
Time synchronization disabled. The Time
Stamp counter value is not reset upon re-
dominate state is “0”; recessive state is “1”
dominate state is “1”; recessive state is “0”
CRX
BUFFLOC
TSTPEN
ception or transmission of a message to/
from buffer 0.
Time synchronization enabled. The Time
Stamp counter value is reset upon recep-
tion or transmission of a message to/from
buffer 0.
Data Direction. By setting or resetting the DDIR
bit, the user can select the direction the data
bytes are transmitted and received. The
CR16CAN transmits and receives the CAN
data byte Data1 first and the data byte Data8
last (Data1, Data2,...,Data7, Data8).
If DDIR is set to “0” the data contents of a re-
ceived message is stored with the first byte at
the highest data address and the last data at
the lowest data address (see Figure 69). The
same applies for transmitted data.
“1”
DDIR
Figure 69.
Data Direction Bit set to ‘0’
0A
16
08
16
06
16
04
16
Data Bytes
Data8
Data7
Data6
Data5
Data4
Data3
Data2
Data1
ADDR offset
Data1
Data3
Data2
Data4
Data5
Data6
Data7
Data8
t
Sequence of Data Bytes on the Bus
Storage of Data Bytes
in the Buffer Memory
ID
CRC
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