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| 型號： | CR16HCT9 |
| 文件頁數(shù)： | 37/157頁 |
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| 代理商： | CR16HCT9 |
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a maskable interrupt or a non-maskable interrupt (NMI). All
of the maskable hardware wake-up events are gathered and
processed by the Multi-Input Wake-Up Module, which is ac-
tive in all modes. Once a wake-up event is detected, it is
latched until an interrupt acknowledge cycle occurs or a reset
is applied.
A wake-up event causes a transition to the Active mode and
restores normal clock operation, but does not start execution
of the program. It is the interrupt service routine associated
with the wake-up source (MIWU16 or NMI) that causes actu-
al program execution to resume.
11.6.1
Power Management Control/Status Register
(PMCSR)
The Power Management Control/Status Register (PMCSR)
is a byte-wide, read/write register that controls the operating
power mode (Active, Power Save, Idle, or Halt) and enables
or disables the high-frequency oscillator in the Power Save
and Idle modes. The two most significant bits, OLFC and
OHFC, are read-only status bits controlled by the hardware.
Upon reset, the non-reserved bits of this register are cleared.
The format of the register is shown below.
7
6
5
4
OLFC OHFC WBPSM Reserved HALT IDLE DHF PSM
PSM
Power Save Mode. When this bit is 0, the de-
vice operates in the Active mode. Writing a 1 to
this bit position puts the device into the Power
Save mode, either immediately or upon execu-
tion of the next WAIT instruction, depending on
the WBPSM bit.
The PSM bit can be set and cleared by the soft-
ware. It is also cleared by the hardware when a
hardware wake-up event is detected.
Disable High-Frequency Oscillator. This bit en-
ables (0) or disables (1) the high-frequency os-
cillator in the Power Save or Idle mode. (The
high-frequency oscillator is always enabled in
Active mode and always disabled in Halt mode,
regardless of this bit settings.) The DHF bit is
cleared automatically when a hardware wake-
up event is detected.
Idle Mode. When this bit is set and the device
is in Power Save mode, the device enters the
DHF
IDLE
Idle mode upon execution of a WAIT instruc-
tion. In order to enter the Idle mode directly
from the Active mode, the WBPSM bit must be
set before the WAIT instruction is executed.
The IDLE bit can be set and cleared by the soft-
ware. When a hardware wake-up event is de-
tected, this bit is cleared automatically and the
device returns to the Active mode.
Halt Mode. When this bit is set and the device
is in Idle mode, the device enters the Halt mode
upon execution of a WAIT instruction. In order
to enter the Halt mode directly from the Active
mode, the WBPSM bit must be set before the
WAIT instruction is executed.
The Halt bit can be set and cleared by the soft-
ware. When a hardware wake-up event is de-
tected, this bit is cleared automatically and the
device returns to the Active mode.
Wait Before Entering Power Save Mode. When
the CPU writes a 1 to the PSM bit, the WBPSM
determines when the transition from Active to
Power Save mode is done. If the WBPSM bit is
0, the switch to Power Save mode is initiated
immediately; the PSM bit in the register is set
to 1 upon completion of the switch to Power
Save mode. If the WBPSM bit is 1, the device
continues to operate in Active mode until the
next WAIT instruction, and then enters the
Power Save mode. In this case, the PSM bit is
set to 1 immediately, even if a WAIT instruction
has not yet been executed.
In the Active mode, the WBPSM bit must be set
in order to enter the Idle or Halt mode.
Oscillating High-Frequency Clock. This read-
only bit indicates the status of the high-frequen-
cy clock. If this bit is 1, the high-frequency clock
is available and stable. If this bit is 0, the high-
frequency clock is either disabled, not available
to the Power Management Module, or operat-
ing but not yet stable. The device can switch to
the Active mode only when this bit is 1.
Oscillating Low-Frequency Clock. This read-
only bit indicates the status of the low-frequen-
cy (slow) clock. If this bit is 1, it indicates that
the slow clock is running and stable. The slow
clock can be either the prescaled fast clock (the
default) or the external oscillator (if selected).
The Dual Clock module will not allow a transi-
tion to the slow crystal mode unless the slow
crystal is operating, so this bit should be 1 un-
der normal circumstances.
The device can switch from the Active mode to
the Power Save or Idle mode only if the OLFC
bit is 1. There is no such restriction on switch-
ing to the Halt mode.
HALT
WBPSM
OHFC
OLFC
Figure 6.
Power Modes and Transitions
3
2
1
0
Active
Power Save
IDLE =1
and WAIT
Idle
Halt
PSM =1
HW event
or PSM =0
HALT =1
and WAIT
HW event
Reset
HW event
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