參數(shù)資料
型號(hào): CS42L51-DNZ
廠商: Cirrus Logic Inc
文件頁數(shù): 20/43頁
文件大?。?/td> 0K
描述: IC CODEC STEREO W/HDPN AMP 32QFN
標(biāo)準(zhǔn)包裝: 60
類型: 立體聲音頻
數(shù)據(jù)接口: 串行
分辨率(位): 24 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
動(dòng)態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 98 / 98
電壓 - 電源,模擬: 1.8V,2.5V
電壓 - 電源,數(shù)字: 1.8V,2.5V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-QFN
供應(yīng)商設(shè)備封裝: 32-QFN 裸露焊盤(5x5)
包裝: 托盤
產(chǎn)品目錄頁面: 754 (CN2011-ZH PDF)
配用: 598-1005-ND - BOARD EVAL FOR CS42L51 CODEC
其它名稱: 598-1627
DS679F1
27
CS42L51
4.2
Hardware Mode
A limited feature-set is available when the CODEC powers up in Hardware Mode (see “Recommended Pow-
er-Up Sequence” on page 41) and may be controlled via stand-alone control pins. Table 2 shows a list of
functions/features, the default configuration and the associated stand-alone control available.
Hardware Mode Feature/Function Summary
Feature/Function
Default Configuration
Stand-Alone Control
Note
Power Control
CODEC
PGAx
ADCx
DACx
MIC Bias
MICx Pre-amplifier
Powered Up
Powered Down
--
Auto-Detect
Enabled
-
Speed Mode
Serial Port Slave
Serial Port Master
Auto-Detect Speed Mode
Single-Speed Mode
--
MCLK Divide
(Selectable)
see Section
Serial Port Master / Slave Selection
(Selectable)
see Section
Interface Control
ADC
DAC
(Selectable)
see Section
ADC Volume & Gain
Digital Boost
Soft Ramp
Zero Cross
Invert
PGAx
Attenuator
ALC
Noise Gate
Disabled
0 dB
Disabled
--
ADCx High-Pass Filter
ADCx High-Pass Filter Freeze
Enabled
Continuous DC Subtraction
--
Line/MIC Input Select
AIN1A to PGAA
AIN1B to PGAB
--
DAC Volume & Gain
HP Gain
AOUTx Volume
Invert
Soft Ramp
Zero Cross
G = 0.6047
0 dB
Disabled
Enabled
Disabled
--
DAC De-Emphasis
(Selectable)
see Section
Signal Processing Engine (SPE)
Mix
Beep
Tone Control
Peak Detect and Limiter
Disabled
--
Data Selection
Data Input (PCM) to DAC
-
Channel Mix
ADC
DAC
ADCA = L; ADCB = R
PCMA = L; PCMB = R
--
Charge Pump Frequency
(64xFs)/7
-
Table 2. Hardware Mode Feature Summary
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