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參數(shù)資料
| 型號： | CS42L51-DNZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 38/43頁 |
| 文件大小： | 0K |
| 描述： | IC CODEC STEREO W/HDPN AMP 32QFN |
| 標準包裝： | 60 |
| 類型： | 立體聲音頻 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 2 / 2 |
| 三角積分調(diào)變： | 是 |
| 動態(tài)范圍，標準 ADC / DAC (db)： | 98 / 98 |
| 電壓 - 電源，模擬： | 1.8V，2.5V |
| 電壓 - 電源，數(shù)字： | 1.8V，2.5V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-QFN |
| 供應商設備封裝： | 32-QFN 裸露焊盤（5x5） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 754 (CN2011-ZH PDF) |
| 配用： | 598-1005-ND - BOARD EVAL FOR CS42L51 CODEC |
| 其它名稱： | 598-1627 |
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DS679F1
43
CS42L51
4.10
Software Mode
The control port is used to access the registers allowing the CODEC to be configured for the desired oper-
ational modes and formats. The operation of the control port may be completely asynchronous with respect
to the audio sample rates. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
The control port operates in two modes: SPI and IC, with the CODEC acting as a slave device. Software
Mode is selected if there is a high-to-low transition on the AD0/CS pin after the RESET pin has been brought
high. IC Mode is selected by connecting the AD0/CS pin through a resistor to VL or DGND, thereby per-
manently selecting the desired AD0 bit address state.
4.10.1
SPI Control
In Software Mode, CS is the CS42L51 chip-select signal, CCLK is the control port bit clock (input into the
CS42L51 from the microcontroller), CDIN is the input data line from the microcontroller. Data is clocked
in on the rising edge of CCLK. The CODEC will only support write operations. Read request will be ig-
nored.
Figure 23 shows the operation of the control port in Software Mode. To write to a register, bring CS low.
The first seven bits on CDIN form the chip address and must be 1001010. The eighth bit is a read/write
indicator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP),
which is set to the address of the register that is to be updated. The next eight bits are the data which will
be placed into the register designated by the MAP.
There is MAP auto-increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero,
the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will auto-increment
after each byte is read or written, allowing block reads or writes of successive registers.
4.10.2
IC Control
In IC Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.
There is no CS pin. Pin AD0 forms the least significant bit of the chip address and should be connected
through a resistor to VL or DGND as desired. The state of the pin is sensed while the CS42L51 is being
reset.
The signal timings for a read and write cycle are shown in Figure 24 and Figure 25. A Start condition is
defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while
the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS42L51
after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write).
The upper 6 bits of the 7-bit address field are fixed at 100101. To communicate with a CS42L51, the chip
address field, which is the first byte sent to the CS42L51, should match 100101 followed by the setting of
the AD0 pin. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the
Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read,
4
5
6
7
CCLK
CHIP ADDRESS (WRITE)
MAP BYTE
DATA
1
0
1
0
1
0
CDIN
INCR
6
5
4
3
2
1
0
7
6
1
0
1
2
3
8
9
12
16 17
10 11
13 14 15
DATA +n
CS
7
6
1
0
Figure 23. Control Port Timing in SPI Mode
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS42L51-DNZR | 功能描述:接口—CODEC IC LV Stereo Codec F Digital Audio Apps RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| CS42L52 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:2Low-power, Stereo CODEC w/ Headphone & Speaker Amps |
| CS42L52_08 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:2Low-power, Stereo CODEC w/ Headphone & Speaker Amps |
| CS42L52-CNZ | 功能描述:接口—CODEC Low Power Stereo CODEC w/ HP+Spkr Amp RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| CS42L52-CNZ/B1 | 制造商:Cirrus Logic 功能描述: |
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